qdr_lc_top.v

XILINX memory interface generator. XILINX的外部存储器接口。

	                           .Sortie(Cout_WDataL),
	                           .counter(Counter_outL))/* synthesis syn_noprune =1 */; 


always@(posedge GCLK0)
begin
  if(Reset_CLK0)
    GCLK0_2 <= 0; 
  else 
    GCLK0_2 <= ~GCLK0_2;
end


	                             
//*****************************************************************************************
// Generate addresses using a conter, from address 0, out of CLK0/2 and ~CLK0/2
//*****************************************************************************************  	    

counter_262144 AddrGeneR ( .COut2(AddrR), 
                          .inc(~GCLK0_2),
                          .reset(ResetCount ));   
                          


                          
counter_262144 AddrGeneW ( .COut2(AddrW), //Addr
                        .inc(GCLK0_2),
                          .reset(ResetCount ));     



//*****************************************************************************************
// Delay at power up to leave time for the QDR II SRAM to lock its DLL
//*****************************************************************************************  
delay StartTest( .Si_In(DCM_LOCKED),
                 .Si_Out(ThisIsAGo),
                 .Clock(GCLK0),
                 .Reset(Reset_CLK0));    

//*****************************************************************************************
// Generation of the reference data to compare written adn read data
//*****************************************************************************************               
counter_4 Data_Check_Gene ( .counter(To_concatenate), 
                            .inclock(GCLK90),
                            .reset(~FD_UserDataValid));   


                     
concat2to36Data Concatenate_Test ( .inclock(GCLK90),
	                .Sortie(Reference_Data),
	                .counter(To_concatenate));   
                       
//*****************************************************************************************                       
// User input buffer not declared in interface
//*****************************************************************************************
OBUF_LVDCI_25 INST_OBUF_Result_D0 (.O(Result_Reg), .I(Result_BUF)); 

//*****************************************************************************************
// Comparator of read data
//*****************************************************************************************
always @ ( posedge GCLK0)
 begin
 if (Reset_CLK0)
   Result <= 1'b0;
  else begin
   if ((FD_UserDataValid) && (FD_Data_R[143:108] == Reference_Data[71:36]) && 
   			     (FD_Data_R[107:72] == Reference_Data[35:0]) &&
   			     (FD_Data_R[71:36] == Reference_Data[71:36]) && 
   			     (FD_Data_R[35:0] == Reference_Data[35:0]))

    Result <= 1'b1;
   else
    Result <= 1'b0;
  end
end

always @ (posedge GCLK0)
 begin: SYNC_Result
   Result_BUF <= Result;
   Reference_Data_BUF <= Reference_Data[0];
  end

//*****************************************************************************************
// Test design state machine
//*****************************************************************************************
always @ (DCM_LOCKED or ThisIsAGo or CurrentState or AddrW or AddrR or W_n or R_n or Status_Ctrl_Operation)
 begin: COMB
 	NextState <= Start;
   		case (CurrentState)
    		Start: begin
     			if (DCM_LOCKED)
      				NextState <= GetReady;
     			else
      				NextState <= Start;
     			end
     			
    		GetReady: begin
     			if (ThisIsAGo)
      				if (Status_Ctrl_Operation)
       					NextState <= ReadCycle;
      				else 
       					NextState <= WriteCycle;
     			else
      				NextState <= GetReady;      
    			end
    			
    		WriteCycle: begin
     			if ((AddrW == 18'h0001F) && (R_n == 1'b1)) //0001F
      				NextState <= Start;
     			else
      				NextState <= WriteCycle;
     			end
     			
    		ReadCycle: begin
     			if ((AddrR == 18'h0001E) && (W_n == 1'b1))  //0001E
			      NextState <= Start;
     			else
     				NextState <= ReadCycle;
     			end
     			
    		endcase
   end
     
//*****************************************************************************************
// Synchronous state machine   
//*****************************************************************************************  
always @ (posedge GCLK0)
begin: SEQ
	if (Reset_CLK0)
   		CurrentState <= Start;
  	else
   		CurrentState <= NextState;
end
       
always @ (CurrentState or Status_Ctrl_Operation_buf)


begin: OUT_LOGIC
	case (CurrentState)
   		Start: begin
   			ResetCount <= 1'b1;
    			R_n <= 1'b1;
    			W_n <= 1'b1;
    			Status_Ctrl_Operation <= Status_Ctrl_Operation_buf;
   			end
   			
   		GetReady: begin
    			ResetCount <= 1'b1;
    			R_n <= 1'b1;
    			W_n <= 1'b1;
    			Status_Ctrl_Operation <= Status_Ctrl_Operation_buf;
   			end
   			
   		WriteCycle: begin
    			ResetCount <= 1'b0;
    			R_n <= 1'b1;
    			W_n <= 1'b0;
    			Status_Ctrl_Operation <= 1'b1;
   			end
   			
   		ReadCycle: begin
    			ResetCount <= 1'b0;
    			R_n <= 1'b0;
    			W_n <= 1'b1;
    			Status_Ctrl_Operation <= 1'b0;
   			end
   			
   		default: begin
    			ResetCount <= 1'b1;
    			R_n <= 1'b1;
    			W_n <= 1'b0;
    			Status_Ctrl_Operation <= 1'b0;
   			end
  endcase
 end
 
 always @ (posedge GCLK0)
 begin: COMB_to_SEQ
 	if (Reset_CLK0)
   		Status_Ctrl_Operation_buf <= 1'b0;
  	else
   		Status_Ctrl_Operation_buf <= Status_Ctrl_Operation;
  	end

endmodule

//*****************************************************************************************
// Counter with generation of data to be written to memory
//*****************************************************************************************
module counter_4 (counter, inclock, reset);
 output [1:0] counter;
 input inclock;
 input reset;
	
 reg [1:0] counter;

 always @ (posedge inclock) begin 
  if (reset)
   counter <= 2'b00;
    else
      counter <= counter + 2'b01;
   end
endmodule

module concat2to36Data(Sortie, inclock, counter);
 output [71:0] Sortie;
 input inclock;
 input [1:0] counter;

 reg [71:0] Sortie/* synthesis syn_keep =1 */;
 
  always @ (posedge inclock) begin
   Sortie <= {36{counter}};
  end
  
endmodule

module counter_262144 (COut2, inc, reset);
	output [17:0] COut2;
	input inc;
	input reset;    
	
	reg [17:0] COut2;

	always @ (posedge inc) begin 
		if (reset)
			COut2 <= 18'h00000;
		else begin
			if (COut2 == 18'h0001F) //262142
				COut2 <= 18'h00000;
			else
				COut2 <= COut2 + 1'b1;
		end
	end

	
endmodule

module delay(Si_In, Si_Out, Clock, Reset);
 input Si_In;
 output Si_Out;
 input Clock;
 input Reset;
 
 reg [9:0] counter;
 reg Si_Out;
 
//*****************************************************************************************
// Counter used to delay the start of the test program
//*****************************************************************************************
 always @ (negedge Clock) begin
  if (Reset) begin
   counter <= 10'h000;
   Si_Out <= 1'b0;
  end
  else begin 
   if (Si_In) begin
    if (counter == 10'h3FF)
     Si_Out <= 1'b1;
   else begin
    counter <= counter + 1'b1;
    Si_Out <= 1'b0;
    end
   end
  end
 end 
endmodule