qdr2_burst_4_body.v

XILINX memory interface generator. XILINX的外部存储器接口。

//*****************************************************************************************
//** 
//**  www.xilinx.com               Copyright (c) 1984-2004 Xilinx, Inc. All rights reserved
//** 
//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
//**
//*****************************************************************************************
//**
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// This module is the top level architecture for the memory interface design.
// The signals connections are describled in the application note. 
// The ports naming convention is as follows:
// - user side: USER_INSTNAME
// - memory side: QDR_INSTNAME

`timescale 1 ns/1 ps

module qdr2_burst_4_body (USER_DWL, 
                          USER_DWH,
                          USER_Q, 
                          CLK_BUF,
                          CLK0E,
                          CLK90E,
                          CLK180E,
                          CLK270E,
                          R_n_recapture,
                          LOCKED_DCM_PRI,
                          USER_R_n, 
                          USER_W_n, 
                          USER_RESET, 
                          USER_DATA_VALID,
                          QDR_Q,
                          QDR_D,
                          sys_rst180,
                          QDR_CQ0,
                          QDR_CQ0_n,
                          QDR_CQ1,
                          QDR_CQ1_n,
                          
                          TEST_RESET_0);

// Parameters

   parameter data_bits = 72 -1; // Size of the data bus -1
   parameter addr_bits = 18 -1; // Size of the address bus -1
   
                                                                                                                                                                                                                                                                                                                                                      
	input  [data_bits : 0] USER_DWL;
	input  [data_bits : 0] USER_DWH;
        output [143        : 0] USER_Q;
	input R_n_recapture;
	input CLK_BUF;
	input CLK0E;
	input CLK90E;
	input CLK180E;
	input CLK270E;
              
	input LOCKED_DCM_PRI;
        input USER_RESET;
        input           USER_R_n;
        input           USER_W_n;
        output          USER_DATA_VALID;
        output sys_rst180;
        
        output [data_bits : 0] QDR_D;
        input  [data_bits : 0] QDR_Q;
        input  QDR_CQ0;
        input  QDR_CQ0_n;
        input  QDR_CQ1;
        input  QDR_CQ1_n;
        
        output TEST_RESET_0;    


	wire [3:0] CQ;
	wire RESET;                                                      
	wire GND;                                                        
	wire HIGH;                                                                                                                                                            
	wire O_DDR_K_OBUF;
	wire O_DDR_K_n_OBUF;                                 
	wire ReadInProgress;                                  
	wire LOCKED_DCM_PRI;
	wire R_n_FD;                                                      
	wire W_BAR;
	wire R_BAR;                                               
	wire [data_bits : 0] D_data; 
        reg [addr_bits : 0] ADR;
        wire noReadCurrent;
        wire [4:0] selTap;

	wire R_n_recapture;
	wire MUX_ADDR;
	
	reg sys_rst0_o; 
        reg sys_rst0_1; 
        reg sys_rst0;   
	reg sys_rst90_o;
	reg sys_rst90_1;
	reg sys_rst90;
	reg sys_rst180_o;
	reg sys_rst180_1;
	reg sys_rst180;
	reg sys_rst270_o;
	reg sys_rst270_1;
	reg sys_rst270;
	
// Signals assigment                                                                                     
        assign GND = 1'b0;                                               
        assign HIGH = 1'b1;                                                                                  
        assign noReadCurrent = ~((~USER_R_n) || (USER_DATA_VALID)); // uses output of the user FIFO: make sure that data are automatically pulled out of the FIFO or this needs to ne changed.
        assign CQ = {QDR_CQ1_n,QDR_CQ1,QDR_CQ0_n,QDR_CQ0};
        assign RESET = USER_RESET;
        assign TEST_RESET_0 = sys_rst0;

       

// Generation of the reset signal in the different clock domains
always @ (posedge CLK0E) begin
  if ((RESET == 1'b1) || (LOCKED_DCM_PRI == 1'b0)) begin
      sys_rst0_o <= 1'b1;
      sys_rst0_1 <= 1'b1;
      sys_rst0   <= 1'b1;
  end
   else begin
      sys_rst0_o <= 1'b0;
      sys_rst0_1 <= sys_rst0_o;
      sys_rst0   <= sys_rst0_1;
  end
end
 
always @ (posedge CLK90E) begin
  if ((RESET == 1'b1) || (LOCKED_DCM_PRI == 1'b0)) begin
      sys_rst90_o <= 1'b1;
      sys_rst90_1 <= 1'b1;
      sys_rst90   <= 1'b1;
  end
   else begin
      sys_rst90_o <= 1'b0;
      sys_rst90_1 <= sys_rst90_o;
      sys_rst90   <= sys_rst90_1;
  end
end
 
always @ (posedge CLK180E) begin 
  if ((RESET == 1'b1) || (LOCKED_DCM_PRI == 1'b0)) begin
      sys_rst180_o <= 1'b1;
      sys_rst180_1 <= 1'b1;
      sys_rst180   <= 1'b1;
  end        
   else       
  begin      
      sys_rst180_o <= 1'b0;
      sys_rst180_1 <= sys_rst180_o;
      sys_rst180   <= sys_rst180_1;
  end
end

always @ (posedge CLK270E) begin
  if ((RESET == 1'b1) || (LOCKED_DCM_PRI == 1'b0)) begin
      sys_rst270_o <= 1'b1;
      sys_rst270_1 <= 1'b1;
      sys_rst270   <= 1'b1;
  end      
   else     
  begin    
      sys_rst270_o <= 1'b0;
      sys_rst270_1 <= sys_rst270_o;
      sys_rst270   <= sys_rst270_1;
  end
end


// Write data bus to QDR II SRAM device                                                                    
OBUF_HSTL_II_18 INST_QDR_OBUF_DWRITE_[data_bits:0]  (.I(D_data[data_bits:0]) ,.O(QDR_D[data_bits:0]) );

                                                                         
// Write operation module                                                                                                       
write_burst_4 INST_Write  
			(.CLK90		(CLK90E), 
			 .CLK270		(CLK270E),
			 .D0		(USER_DWH), 
			 .D1		(USER_DWL), 
			 .Q		(D_data), 
			 .CLK180		(CLK180E), 
			 .RESET		(RESET)); // RAKCHOPR -- Added reset port

//*****************************************************************************************
// Calibration circuit
//*****************************************************************************************
FD FD_NoRead (  .Q(CalNoRead), 
		.D(noReadCurrent), 
		.C(CLK0E));

wire CalNoRead; //CalNoRead out of CLK0 enables tap change from the calibration circuit when there is no read current

cal_top cal_inst 
		(.clk		(CLK_BUF), 
		 .clk0		(CLK0E), 
		 .clk0dcmlock		(LOCKED_DCM_PRI), 
		 .reset		(sys_rst0), 
		 .okToSelTap		(CalNoRead), 
		 .tapForDqs		(selTap));

// Read datapath implementation
data_path Read_data_path 
		( .clk			(CLK0E), 
		  .clk90			(CLK90E), 
		  .clk180			(CLK180E), 
		  .clk270			(CLK270E), 
		  .reset			(sys_rst0), 
		  .reset90			(sys_rst90), 
		  .reset180			(sys_rst180), 
		  .reset270			(sys_rst270), 
		  .rst_cq_div			(R_n_recapture), 
		  .delay_sel			(selTap), 
		  .u_data_val			(USER_DATA_VALID), 
		  .qdr2_cq			(CQ), 
		  .qdr2_q			(QDR_Q), 
		  .user_output_data			(USER_Q));    
endmodule