📄 data_path.v
字号:
.transfer_done2(transfer_done_22),
.transfer_done3(transfer_done_23));
qdr2_transfer_done qdr2_transfer_done3 ( .clk0(clk),
.clk90(clk90),
.clk180(clk180),
.clk270(clk270),
.reset(reset_r),
.reset90(reset90_r),
.reset180(reset180_r),
.reset270(reset270_r),
.cq_div(cq_div_transfert_3_col1),
.transfer_done0(transfer_done_30),
.transfer_done1(transfer_done_31),
.transfer_done2(transfer_done_32),
.transfer_done3(transfer_done_33));
//****************************************************************************************************************
// Generation of the synchronous CE for the data capture FD.
//****************************************************************************************************************
FD FD_R_n_00_DC (.Q(CE_R_FB00),
.C(cq_delayed_col1[0]), //changed col1 to col0
.D(rst_cq_div));
FD FD_R_n_01_DC (.Q(CE_R_FB01),
.C(~cq_delayed_col0[0]),
.D(CE_R_FB00));
FD FD_R_n_02_DC (.Q(CE_R_FB02),
.C(cq_delayed_col1[0]), //changed col1 to col0
.D(CE_R_FB00));
FD FD_R_n_03_DC (.Q(CE_R_FB03),
.C(~cq_delayed_col0[0]),
.D(CE_R_FB01));
/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
FD FD_R_n_10_DC (.Q(CE_R_FB10),
.C(cq_delayed_col1[2]), //changed col1 to col0
.D(rst_cq_div));
FD FD_R_n_11_DC (.Q(CE_R_FB11),
.C(~cq_delayed_col0[2]),
.D(CE_R_FB10));
FD FD_R_n_12_DC (.Q(CE_R_FB12),
.C(cq_delayed_col1[2]), //changed col1 to col0
.D(CE_R_FB10));
FD FD_R_n_13_DC (.Q(CE_R_FB13),
.C(~cq_delayed_col0[2]),
.D(CE_R_FB11));
//******************************************************************************************************************************
// Q Data bits instantiations (36-bits)
//******************************************************************************************************************************
qdr2_qbit_cq qdr2_qbit_0 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[0] ), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[0] ), .fbit_1(fbit_1[0] ), .fbit_2(fbit_2[0] ), .fbit_3(fbit_3[0] ));
qdr2_qbit_cq qdr2_qbit_1 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[1] ), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[1] ), .fbit_1(fbit_1[1] ), .fbit_2(fbit_2[1] ), .fbit_3(fbit_3[1] ));
qdr2_qbit_cq qdr2_qbit_2 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[2] ), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[2] ), .fbit_1(fbit_1[2] ), .fbit_2(fbit_2[2] ), .fbit_3(fbit_3[2] ));
qdr2_qbit_cq qdr2_qbit_3 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[3] ), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[3] ), .fbit_1(fbit_1[3] ), .fbit_2(fbit_2[3] ), .fbit_3(fbit_3[3] ));
qdr2_qbit_cq qdr2_qbit_4 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[4] ), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[4] ), .fbit_1(fbit_1[4] ), .fbit_2(fbit_2[4] ), .fbit_3(fbit_3[4] ));
qdr2_qbit_cq qdr2_qbit_5 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[5] ), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[5] ), .fbit_1(fbit_1[5] ), .fbit_2(fbit_2[5] ), .fbit_3(fbit_3[5] ));
qdr2_qbit_cq qdr2_qbit_6 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[6] ), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[6] ), .fbit_1(fbit_1[6] ), .fbit_2(fbit_2[6] ), .fbit_3(fbit_3[6] ));
qdr2_qbit_cq qdr2_qbit_7 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[7] ), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[7] ), .fbit_1(fbit_1[7] ), .fbit_2(fbit_2[7] ), .fbit_3(fbit_3[7] ));
qdr2_qbit_cq qdr2_qbit_8 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[8] ), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[8] ), .fbit_1(fbit_1[8] ), .fbit_2(fbit_2[8] ), .fbit_3(fbit_3[8] ));
qdr2_qbit_cq qdr2_qbit_9 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[9] ), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[9] ), .fbit_1(fbit_1[9] ), .fbit_2(fbit_2[9] ), .fbit_3(fbit_3[9] ));
qdr2_qbit_cq qdr2_qbit_10 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[10]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[10]), .fbit_1(fbit_1[10]), .fbit_2(fbit_2[10]), .fbit_3(fbit_3[10]));
qdr2_qbit_cq qdr2_qbit_11 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[11]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[11]), .fbit_1(fbit_1[11]), .fbit_2(fbit_2[11]), .fbit_3(fbit_3[11]));
qdr2_qbit_cq qdr2_qbit_12 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[12]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[12]), .fbit_1(fbit_1[12]), .fbit_2(fbit_2[12]), .fbit_3(fbit_3[12]));
qdr2_qbit_cq qdr2_qbit_13 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[13]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[13]), .fbit_1(fbit_1[13]), .fbit_2(fbit_2[13]), .fbit_3(fbit_3[13]));
qdr2_qbit_cq qdr2_qbit_14 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[14]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[14]), .fbit_1(fbit_1[14]), .fbit_2(fbit_2[14]), .fbit_3(fbit_3[14]));
qdr2_qbit_cq qdr2_qbit_15 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[15]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[15]), .fbit_1(fbit_1[15]), .fbit_2(fbit_2[15]), .fbit_3(fbit_3[15]));
qdr2_qbit_cq qdr2_qbit_16 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[16]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[16]), .fbit_1(fbit_1[16]), .fbit_2(fbit_2[16]), .fbit_3(fbit_3[16]));
qdr2_qbit_cq qdr2_qbit_17 ( .reset(reset270_r), .cq(cq_delayed_col0[0]), .cq1(cq_delayed_col1[0]), .qdr2_q(qdr2_q[17]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[17]), .fbit_1(fbit_1[17]), .fbit_2(fbit_2[17]), .fbit_3(fbit_3[17]));
qdr2_qbit_cq_bar qdr2_qbit_bar_0 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[18]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[18]), .fbit_1(fbit_1[18]), .fbit_2(fbit_2[18]), .fbit_3(fbit_3[18]));
qdr2_qbit_cq_bar qdr2_qbit_bar_1 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[19]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[19]), .fbit_1(fbit_1[19]), .fbit_2(fbit_2[19]), .fbit_3(fbit_3[19]));
qdr2_qbit_cq_bar qdr2_qbit_bar_2 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[20]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[20]), .fbit_1(fbit_1[20]), .fbit_2(fbit_2[20]), .fbit_3(fbit_3[20]));
qdr2_qbit_cq_bar qdr2_qbit_bar_3 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[21]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[21]), .fbit_1(fbit_1[21]), .fbit_2(fbit_2[21]), .fbit_3(fbit_3[21]));
qdr2_qbit_cq_bar qdr2_qbit_bar_4 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[22]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[22]), .fbit_1(fbit_1[22]), .fbit_2(fbit_2[22]), .fbit_3(fbit_3[22]));
qdr2_qbit_cq_bar qdr2_qbit_bar_5 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[23]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[23]), .fbit_1(fbit_1[23]), .fbit_2(fbit_2[23]), .fbit_3(fbit_3[23]));
qdr2_qbit_cq_bar qdr2_qbit_bar_6 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[24]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[24]), .fbit_1(fbit_1[24]), .fbit_2(fbit_2[24]), .fbit_3(fbit_3[24]));
qdr2_qbit_cq_bar qdr2_qbit_bar_7 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[25]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[25]), .fbit_1(fbit_1[25]), .fbit_2(fbit_2[25]), .fbit_3(fbit_3[25]));
qdr2_qbit_cq_bar qdr2_qbit_bar_8 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[26]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[26]), .fbit_1(fbit_1[26]), .fbit_2(fbit_2[26]), .fbit_3(fbit_3[26]));
qdr2_qbit_cq_bar qdr2_qbit_bar_9 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[27]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[27]), .fbit_1(fbit_1[27]), .fbit_2(fbit_2[27]), .fbit_3(fbit_3[27]));
qdr2_qbit_cq_bar qdr2_qbit_bar_10 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[28]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[28]), .fbit_1(fbit_1[28]), .fbit_2(fbit_2[28]), .fbit_3(fbit_3[28]));
qdr2_qbit_cq_bar qdr2_qbit_bar_11 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[29]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[29]), .fbit_1(fbit_1[29]), .fbit_2(fbit_2[29]), .fbit_3(fbit_3[29]));
qdr2_qbit_cq_bar qdr2_qbit_bar_12 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[30]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[30]), .fbit_1(fbit_1[30]), .fbit_2(fbit_2[30]), .fbit_3(fbit_3[30]));
qdr2_qbit_cq_bar qdr2_qbit_bar_13 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[31]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[31]), .fbit_1(fbit_1[31]), .fbit_2(fbit_2[31]), .fbit_3(fbit_3[31]));
qdr2_qbit_cq_bar qdr2_qbit_bar_14 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[32]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[32]), .fbit_1(fbit_1[32]), .fbit_2(fbit_2[32]), .fbit_3(fbit_3[32]));
qdr2_qbit_cq_bar qdr2_qbit_bar_15 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[33]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[33]), .fbit_1(fbit_1[33]), .fbit_2(fbit_2[33]), .fbit_3(fbit_3[33]));
qdr2_qbit_cq_bar qdr2_qbit_bar_16 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[34]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[34]), .fbit_1(fbit_1[34]), .fbit_2(fbit_2[34]), .fbit_3(fbit_3[34]));
qdr2_qbit_cq_bar qdr2_qbit_bar_17 ( .reset(reset270_r), .cq(cq_delayed_col0[1]), .cq1(cq_delayed_col1[1]), .qdr2_q(qdr2_q[35]), .CE_R_FB0(CE_R_FB00), .CE_R_FB1(CE_R_FB01), .CE_R_FB2(CE_R_FB02), .CE_R_FB3(CE_R_FB03), .fbit_0(fbit_0[35]), .fbit_1(fbit_1[35]), .fbit_2(fbit_2[35]), .fbit_3(fbit_3[35]));
//*************************************************************************************************************************
qdr2_qbit_cq qdr2_qbit_18 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[36] ), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[36] ), .fbit_1(fbit_1[36] ), .fbit_2(fbit_2[36] ), .fbit_3(fbit_3[36] ));
qdr2_qbit_cq qdr2_qbit_19 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[37] ), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[37] ), .fbit_1(fbit_1[37] ), .fbit_2(fbit_2[37] ), .fbit_3(fbit_3[37] ));
qdr2_qbit_cq qdr2_qbit_20 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[38] ), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[38] ), .fbit_1(fbit_1[38] ), .fbit_2(fbit_2[38] ), .fbit_3(fbit_3[38] ));
qdr2_qbit_cq qdr2_qbit_21 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[39] ), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[39] ), .fbit_1(fbit_1[39] ), .fbit_2(fbit_2[39] ), .fbit_3(fbit_3[39] ));
qdr2_qbit_cq qdr2_qbit_22 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[40] ), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[40] ), .fbit_1(fbit_1[40] ), .fbit_2(fbit_2[40] ), .fbit_3(fbit_3[40] ));
qdr2_qbit_cq qdr2_qbit_23 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[41] ), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[41] ), .fbit_1(fbit_1[41] ), .fbit_2(fbit_2[41] ), .fbit_3(fbit_3[41] ));
qdr2_qbit_cq qdr2_qbit_24 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[42] ), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[42] ), .fbit_1(fbit_1[42] ), .fbit_2(fbit_2[42] ), .fbit_3(fbit_3[42] ));
qdr2_qbit_cq qdr2_qbit_25 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[43] ), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[43] ), .fbit_1(fbit_1[43] ), .fbit_2(fbit_2[43] ), .fbit_3(fbit_3[43] ));
qdr2_qbit_cq qdr2_qbit_26 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[44] ), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[44] ), .fbit_1(fbit_1[44] ), .fbit_2(fbit_2[44] ), .fbit_3(fbit_3[44] ));
qdr2_qbit_cq qdr2_qbit_27 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[45] ), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[45] ), .fbit_1(fbit_1[45] ), .fbit_2(fbit_2[45] ), .fbit_3(fbit_3[45] ));
qdr2_qbit_cq qdr2_qbit_28 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[46]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[46]), .fbit_1(fbit_1[46]), .fbit_2(fbit_2[46]), .fbit_3(fbit_3[46]));
qdr2_qbit_cq qdr2_qbit_29 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[47]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[47]), .fbit_1(fbit_1[47]), .fbit_2(fbit_2[47]), .fbit_3(fbit_3[47]));
qdr2_qbit_cq qdr2_qbit_30 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[48]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[48]), .fbit_1(fbit_1[48]), .fbit_2(fbit_2[48]), .fbit_3(fbit_3[48]));
qdr2_qbit_cq qdr2_qbit_31 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[49]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[49]), .fbit_1(fbit_1[49]), .fbit_2(fbit_2[49]), .fbit_3(fbit_3[49]));
qdr2_qbit_cq qdr2_qbit_32 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[50]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[50]), .fbit_1(fbit_1[50]), .fbit_2(fbit_2[50]), .fbit_3(fbit_3[50]));
qdr2_qbit_cq qdr2_qbit_33 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[51]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[51]), .fbit_1(fbit_1[51]), .fbit_2(fbit_2[51]), .fbit_3(fbit_3[51]));
qdr2_qbit_cq qdr2_qbit_34 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[52]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[52]), .fbit_1(fbit_1[52]), .fbit_2(fbit_2[52]), .fbit_3(fbit_3[52]));
qdr2_qbit_cq qdr2_qbit_35 ( .reset(reset270_r), .cq(cq_delayed_col0[2]), .cq1(cq_delayed_col1[2]), .qdr2_q(qdr2_q[53]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[53]), .fbit_1(fbit_1[53]), .fbit_2(fbit_2[53]), .fbit_3(fbit_3[53]));
qdr2_qbit_cq_bar qdr2_qbit_bar_18 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[54]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[54]), .fbit_1(fbit_1[54]), .fbit_2(fbit_2[54]), .fbit_3(fbit_3[54]));
qdr2_qbit_cq_bar qdr2_qbit_bar_19 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[55]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[55]), .fbit_1(fbit_1[55]), .fbit_2(fbit_2[55]), .fbit_3(fbit_3[55]));
qdr2_qbit_cq_bar qdr2_qbit_bar_20 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[56]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[56]), .fbit_1(fbit_1[56]), .fbit_2(fbit_2[56]), .fbit_3(fbit_3[56]));
qdr2_qbit_cq_bar qdr2_qbit_bar_21 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[57]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[57]), .fbit_1(fbit_1[57]), .fbit_2(fbit_2[57]), .fbit_3(fbit_3[57]));
qdr2_qbit_cq_bar qdr2_qbit_bar_22 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[58]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[58]), .fbit_1(fbit_1[58]), .fbit_2(fbit_2[58]), .fbit_3(fbit_3[58]));
qdr2_qbit_cq_bar qdr2_qbit_bar_23 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[59]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[59]), .fbit_1(fbit_1[59]), .fbit_2(fbit_2[59]), .fbit_3(fbit_3[59]));
qdr2_qbit_cq_bar qdr2_qbit_bar_24 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[60]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[60]), .fbit_1(fbit_1[60]), .fbit_2(fbit_2[60]), .fbit_3(fbit_3[60]));
qdr2_qbit_cq_bar qdr2_qbit_bar_25 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[61]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[61]), .fbit_1(fbit_1[61]), .fbit_2(fbit_2[61]), .fbit_3(fbit_3[61]));
qdr2_qbit_cq_bar qdr2_qbit_bar_26 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[62]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[62]), .fbit_1(fbit_1[62]), .fbit_2(fbit_2[62]), .fbit_3(fbit_3[62]));
qdr2_qbit_cq_bar qdr2_qbit_bar_27 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[63]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[63]), .fbit_1(fbit_1[63]), .fbit_2(fbit_2[63]), .fbit_3(fbit_3[63]));
qdr2_qbit_cq_bar qdr2_qbit_bar_28 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[64]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[64]), .fbit_1(fbit_1[64]), .fbit_2(fbit_2[64]), .fbit_3(fbit_3[64]));
qdr2_qbit_cq_bar qdr2_qbit_bar_29 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[65]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[65]), .fbit_1(fbit_1[65]), .fbit_2(fbit_2[65]), .fbit_3(fbit_3[65]));
qdr2_qbit_cq_bar qdr2_qbit_bar_30 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[66]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[66]), .fbit_1(fbit_1[66]), .fbit_2(fbit_2[66]), .fbit_3(fbit_3[66]));
qdr2_qbit_cq_bar qdr2_qbit_bar_31 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[67]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[67]), .fbit_1(fbit_1[67]), .fbit_2(fbit_2[67]), .fbit_3(fbit_3[67]));
qdr2_qbit_cq_bar qdr2_qbit_bar_32 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[68]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[68]), .fbit_1(fbit_1[68]), .fbit_2(fbit_2[68]), .fbit_3(fbit_3[68]));
qdr2_qbit_cq_bar qdr2_qbit_bar_33 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[69]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[69]), .fbit_1(fbit_1[69]), .fbit_2(fbit_2[69]), .fbit_3(fbit_3[69]));
qdr2_qbit_cq_bar qdr2_qbit_bar_34 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[70]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[70]), .fbit_1(fbit_1[70]), .fbit_2(fbit_2[70]), .fbit_3(fbit_3[70]));
qdr2_qbit_cq_bar qdr2_qbit_bar_35 ( .reset(reset270_r), .cq(cq_delayed_col0[3]), .cq1(cq_delayed_col1[3]), .qdr2_q(qdr2_q[71]), .CE_R_FB0(CE_R_FB10), .CE_R_FB1(CE_R_FB11), .CE_R_FB2(CE_R_FB12), .CE_R_FB3(CE_R_FB13), .fbit_0(fbit_0[71]), .fbit_1(fbit_1[71]), .fbit_2(fbit_2[71]), .fbit_3(fbit_3[71]));
//*************************************************************************************************************************
// Distributed RAM 18 bits wide FIFO instantiations (4 FIFOs per strobe, 1 for each fbit0 through 3)
//*************************************************************************************************************************
// FIFOs associated with qdr2_cq(0)
RAM_18D RAM_18D_cq0_fbit0 ( .DPO(fifo_00_data_out), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]), .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(fbit_0[17:0]), .DPRA0(fifo_00_rd_addr[0]), .DPRA1(fifo_00_rd_addr[1]), .DPRA2(fifo_00_rd_addr[2]), .DPRA3(fifo_00_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_00));
RAM_18D RAM_18D_cq0_fbit1 ( .DPO(fifo_01_data_out), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]), .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(fbit_1[17:0]), .DPRA0(fifo_00_rd_addr[0]), .DPRA1(fifo_00_rd_addr[1]), .DPRA2(fifo_00_rd_addr[2]), .DPRA3(fifo_00_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_01));
RAM_18D RAM_18D_cq0_fbit2 ( .DPO(fifo_02_data_out), .A0(fifo_02_wr_addr[0]), .A1(fifo_02_wr_addr[1]), .A2(fifo_02_wr_addr[2]), .A3(fifo_02_wr_addr[3]), .D(fbit_2[17:0]), .DPRA0(fifo_02_rd_addr[0]), .DPRA1(fifo_02_rd_addr[1]), .DPRA2(fifo_02_rd_addr[2]), .DPRA3(fifo_02_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_02));
RAM_18D RAM_18D_cq0_fbit3 ( .DPO(fifo_03_data_out), .A0(fifo_03_wr_addr[0]), .A1(fifo_03_wr_addr[1]), .A2(fifo_03_wr_addr[2]), .A3(fifo_03_wr_addr[3]), .D(fbit_3[17:0]), .DPRA0(fifo_02_rd_addr[0]), .DPRA1(fifo_02_rd_addr[1]), .DPRA2(fifo_02_rd_addr[2]), .DPRA3(fifo_02_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_03));
// FIFOs associated with qdr2_cq(1)
RAM_18D RAM_18D_cq1_fbit0 ( .DPO(fifo_10_data_out), .A0(fifo_10_wr_addr[0]), .A1(fifo_10_wr_addr[1]), .A2(fifo_10_wr_addr[2]), .A3(fifo_10_wr_addr[3]), .D(fbit_0[35:18]), .DPRA0(fifo_00_rd_addr[0]), .DPRA1(fifo_00_rd_addr[1]), .DPRA2(fifo_00_rd_addr[2]), .DPRA3(fifo_00_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_10));
RAM_18D RAM_18D_cq1_fbit1 ( .DPO(fifo_11_data_out), .A0(fifo_11_wr_addr[0]), .A1(fifo_11_wr_addr[1]), .A2(fifo_11_wr_addr[2]), .A3(fifo_11_wr_addr[3]), .D(fbit_1[35:18]), .DPRA0(fifo_00_rd_addr[0]), .DPRA1(fifo_00_rd_addr[1]), .DPRA2(fifo_00_rd_addr[2]), .DPRA3(fifo_00_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_11));
RAM_18D RAM_18D_cq1_fbit2 ( .DPO(fifo_12_data_out), .A0(fifo_12_wr_addr[0]), .A1(fifo_12_wr_addr[1]), .A2(fifo_12_wr_addr[2]), .A3(fifo_12_wr_addr[3]), .D(fbit_2[35:18]), .DPRA0(fifo_02_rd_addr[0]), .DPRA1(fifo_02_rd_addr[1]), .DPRA2(fifo_02_rd_addr[2]), .DPRA3(fifo_02_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_12));
RAM_18D RAM_18D_cq1_fbit3 ( .DPO(fifo_13_data_out), .A0(fifo_13_wr_addr[0]), .A1(fifo_13_wr_addr[1]), .A2(fifo_13_wr_addr[2]), .A3(fifo_13_wr_addr[3]), .D(fbit_3[35:18]), .DPRA0(fifo_02_rd_addr[0]), .DPRA1(fifo_02_rd_addr[1]), .DPRA2(fifo_02_rd_addr[2]), .DPRA3(fifo_02_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_13));
// FIFOs associated with qdr2_cq(2)
RAM_18D RAM_18D_cq2_fbit0 ( .DPO(fifo_20_data_out), .A0(fifo_20_wr_addr[0]), .A1(fifo_20_wr_addr[1]), .A2(fifo_20_wr_addr[2]), .A3(fifo_20_wr_addr[3]), .D(fbit_0[53:36]), .DPRA0(fifo_00_rd_addr[0]), .DPRA1(fifo_00_rd_addr[1]), .DPRA2(fifo_00_rd_addr[2]), .DPRA3(fifo_00_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_20));
RAM_18D RAM_18D_cq2_fbit1 ( .DPO(fifo_21_data_out), .A0(fifo_21_wr_addr[0]), .A1(fifo_21_wr_addr[1]), .A2(fifo_21_wr_addr[2]), .A3(fifo_21_wr_addr[3]), .D(fbit_1[53:36]), .DPRA0(fifo_00_rd_addr[0]), .DPRA1(fifo_00_rd_addr[1]), .DPRA2(fifo_00_rd_addr[2]), .DPRA3(fifo_00_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_21));
RAM_18D RAM_18D_cq2_fbit2 ( .DPO(fifo_22_data_out), .A0(fifo_22_wr_addr[0]), .A1(fifo_22_wr_addr[1]), .A2(fifo_22_wr_addr[2]), .A3(fifo_22_wr_addr[3]), .D(fbit_2[53:36]), .DPRA0(fifo_02_rd_addr[0]), .DPRA1(fifo_02_rd_addr[1]), .DPRA2(fifo_02_rd_addr[2]), .DPRA3(fifo_02_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_22));
RAM_18D RAM_18D_cq2_fbit3 ( .DPO(fifo_23_data_out), .A0(fifo_23_wr_addr[0]), .A1(fifo_23_wr_addr[1]), .A2(fifo_23_wr_addr[2]), .A3(fifo_23_wr_addr[3]), .D(fbit_3[53:36]), .DPRA0(fifo_02_rd_addr[0]), .DPRA1(fifo_02_rd_addr[1]), .DPRA2(fifo_02_rd_addr[2]), .DPRA3(fifo_02_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_23));
// FIFOs associated with qdr2_cq(3)
RAM_18D RAM_18D_cq3_fbit0 ( .DPO(fifo_30_data_out), .A0(fifo_30_wr_addr[0]), .A1(fifo_30_wr_addr[1]), .A2(fifo_30_wr_addr[2]), .A3(fifo_30_wr_addr[3]), .D(fbit_0[71:54]), .DPRA0(fifo_00_rd_addr[0]), .DPRA1(fifo_00_rd_addr[1]), .DPRA2(fifo_00_rd_addr[2]), .DPRA3(fifo_00_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_30));
RAM_18D RAM_18D_cq3_fbit1 ( .DPO(fifo_31_data_out), .A0(fifo_31_wr_addr[0]), .A1(fifo_31_wr_addr[1]), .A2(fifo_31_wr_addr[2]), .A3(fifo_31_wr_addr[3]), .D(fbit_1[71:54]), .DPRA0(fifo_00_rd_addr[0]), .DPRA1(fifo_00_rd_addr[1]), .DPRA2(fifo_00_rd_addr[2]), .DPRA3(fifo_00_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_31));
RAM_18D RAM_18D_cq3_fbit2 ( .DPO(fifo_32_data_out), .A0(fifo_32_wr_addr[0]), .A1(fifo_32_wr_addr[1]), .A2(fifo_32_wr_addr[2]), .A3(fifo_32_wr_addr[3]), .D(fbit_2[71:54]), .DPRA0(fifo_02_rd_addr[0]), .DPRA1(fifo_02_rd_addr[1]), .DPRA2(fifo_02_rd_addr[2]), .DPRA3(fifo_02_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_32));
RAM_18D RAM_18D_cq3_fbit3 ( .DPO(fifo_33_data_out), .A0(fifo_33_wr_addr[0]), .A1(fifo_33_wr_addr[1]), .A2(fifo_33_wr_addr[2]), .A3(fifo_33_wr_addr[3]), .D(fbit_3[71:54]), .DPRA0(fifo_02_rd_addr[0]), .DPRA1(fifo_02_rd_addr[1]), .DPRA2(fifo_02_rd_addr[2]), .DPRA3(fifo_02_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_33));
endmodule
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