data_path.v

XILINX memory interface generator. XILINX的外部存储器接口。

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      begin
        next_state       <= 1'b0;
        fifo_00_rd_addr  <= 4'h0;
        fifo_02_rd_addr  <= 4'h0;
        user_output_data <= 144'd0; 
      end
    else
     case (next_state)      
         1'b0: begin
                if (read_valid_data_1 == 1'b1)
                 begin 
                  next_state <= 1'b1;
                  fifo_00_rd_addr <= fifo_00_rd_addr + 1'b1;
                  user_output_data <= {fifo_30_data_out,fifo_20_data_out,
                  				       fifo_10_data_out,fifo_00_data_out,
                  				       fifo_31_data_out,fifo_21_data_out,
                  				       fifo_11_data_out,fifo_01_data_out};
                 end
                else
                  next_state <= 1'b0;
               end
         1'b1: begin
                if (read_valid_data_2 == 1'b1)
                 begin
                  next_state      <= 1'b0;
                  fifo_02_rd_addr <= fifo_02_rd_addr + 1'b1;
                  user_output_data <= {fifo_32_data_out,fifo_22_data_out,
                  				       fifo_12_data_out,fifo_02_data_out,
                  				       fifo_33_data_out,fifo_23_data_out,
                  				       fifo_13_data_out,fifo_03_data_out};
                 end
                else
                  next_state <= 1'b1;
               end
         default: begin 
                   next_state <= 1'b0;
                   fifo_00_rd_addr <= 4'h0;
                   fifo_02_rd_addr <= 4'h0;
                   user_output_data <= 144'd0;
                  end
     endcase                                             
end                                                

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
     begin                                 
      fifo_11_not_empty_r   <= 1'b0;
      fifo_13_not_empty_r   <= 1'b0;
      rd_data_valid         <= 1'b0;
     end                            
    else
     begin                                                   
      fifo_11_not_empty_r   <= fifo_11_not_empty;
      fifo_13_not_empty_r   <= fifo_13_not_empty;
      rd_data_valid         <= read_valid_data;                
     end                                                
end


/***********************************************************************
// Reset flip-flops
***********************************************************************/

FD rst0_r   ( .Q(reset_r),    .C(clk),    .D(reset) );           
FD rst90_r  ( .Q(reset90_r),  .C(clk90),  .D(reset90) );                 
FD rst180_r ( .Q(reset180_r), .C(clk180), .D(reset180) );                                            
FD rst270_r ( .Q(reset270_r), .C(clk270), .D(reset270) );

//***********************************************************************
// Read Data Capture Module Instantiations
//***********************************************************************
// CQ IOB instantiations
//***********************************************************************

v2p_qdr2_input_buffer  v2p_qdr2_input_buffer0 ( .qdr2_in(qdr2_cq[0]), .read_data_in(cq_int_delay_in0));
v2p_qdr2_input_buffer  v2p_qdr2_input_buffer1 ( .qdr2_in(qdr2_cq[1]), .read_data_in(cq_int_delay_in1));
v2p_qdr2_input_buffer  v2p_qdr2_input_buffer2 ( .qdr2_in(qdr2_cq[2]), .read_data_in(cq_int_delay_in2));
v2p_qdr2_input_buffer  v2p_qdr2_input_buffer3 ( .qdr2_in(qdr2_cq[3]), .read_data_in(cq_int_delay_in3));

//**************************************************************************************************
// CQ Internal Delay Circuit implemented in LUTs
//**************************************************************************************************
              
cq_delay  cq_delay0_col0 ( .clk_in(cq_int_delay_in0), .sel_in(delay_sel), .clk_out(cq_delayed_col0[0])); // Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
cq_delay  cq_delay0_col1 ( .clk_in(cq_int_delay_in0), .sel_in(delay_sel), .clk_out(cq_delayed_col1[0])); // Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
cq_delay  cq_delay1_col0 ( .clk_in(cq_int_delay_in1), .sel_in(delay_sel), .clk_out(cq_delayed_col0[1])); // Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                         
cq_delay  cq_delay1_col1 ( .clk_in(cq_int_delay_in1), .sel_in(delay_sel), .clk_out(cq_delayed_col1[1])); // Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
cq_delay  cq_delay2_col0 ( .clk_in(cq_int_delay_in2), .sel_in(delay_sel), .clk_out(cq_delayed_col0[2])); // Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
cq_delay  cq_delay2_col1 ( .clk_in(cq_int_delay_in2), .sel_in(delay_sel), .clk_out(cq_delayed_col1[2])); // Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
cq_delay  cq_delay3_col0 ( .clk_in(cq_int_delay_in3), .sel_in(delay_sel), .clk_out(cq_delayed_col0[3])); // Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs                         
cq_delay  cq_delay3_col1 ( .clk_in(cq_int_delay_in3), .sel_in(delay_sel), .clk_out(cq_delayed_col1[3])); // Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs


//***************************************************************************************************
// CQ Divide by 2 instantiations
//*************************************************************************************************** 

FD FD_R_n_0 (.Q(rst_cq_div_reg_fd1), .C(cq_delayed_col1[0]), .D(rst_cq_div));
FD FD_R_n_1 (.Q(rst_cq_div_reg_fd2), .C(cq_delayed_col1[2]), .D(rst_cq_div));

qdr2_cq_div  qdr2_cq_div0 ( .cq(cq_delayed_col0[0]), 
				    .cq1(cq_delayed_col1[0]), 
				    .rst_cq_div(rst_cq_div_reg_fd1), 
				    .cq_tranfert_col1(cq_div_transfert_0_col0), 
				    .cq_tranfert_col0(cq_div_transfert_0_col1));

qdr2_cq_bar_div  qdr2_cq_bar_div0 ( .cq(cq_delayed_col0[1]), 
						.cq1(cq_delayed_col1[1]), 
						.rst_cq_div(rst_cq_div_reg_fd1), 
						.cq_tranfert_col1(cq_div_transfert_1_col0), 
						.cq_tranfert_col0(cq_div_transfert_1_col1));

qdr2_cq_div  qdr2_cq_div1 ( .cq(cq_delayed_col0[2]), 
				    .cq1(cq_delayed_col1[2]), 
				    .rst_cq_div(rst_cq_div_reg_fd2), 
				    .cq_tranfert_col1(cq_div_transfert_2_col0), 
				    .cq_tranfert_col0(cq_div_transfert_2_col1));

qdr2_cq_bar_div  qdr2_cq_bar_div1 ( .cq(cq_delayed_col0[3]), 
						.cq1(cq_delayed_col1[3]), 
						.rst_cq_div(rst_cq_div_reg_fd2), 
						.cq_tranfert_col1(cq_div_transfert_3_col0), 
						.cq_tranfert_col0(cq_div_transfert_3_col1));


//****************************************************************************************************************
// Transfer done instantiations (One instantiation per strobe)
//****************************************************************************************************************         
 
qdr2_transfer_done  qdr2_transfer_done0 ( .clk0(clk), 
							.clk90(clk90), 
							.clk180(clk180), 
							.clk270(clk270), 
							.reset(reset_r), 
							.reset90(reset90_r), 
							.reset180(reset180_r), 
							.reset270(reset270_r), 
							.cq_div(cq_div_transfert_0_col1), 
							.transfer_done0(transfer_done_00), 
							.transfer_done1(transfer_done_01), 
							.transfer_done2(transfer_done_02), 
							.transfer_done3(transfer_done_03));

qdr2_transfer_done  qdr2_transfer_done1 ( .clk0(clk), 
							.clk90(clk90), 
							.clk180(clk180), 
							.clk270(clk270), 
							.reset(reset_r), 
							.reset90(reset90_r), 
							.reset180(reset180_r), 
							.reset270(reset270_r), 
							.cq_div(cq_div_transfert_1_col1), 
							.transfer_done0(transfer_done_10), 
							.transfer_done1(transfer_done_11), 
							.transfer_done2(transfer_done_12), 
							.transfer_done3(transfer_done_13));

qdr2_transfer_done  qdr2_transfer_done2 ( .clk0(clk), 
							.clk90(clk90), 
							.clk180(clk180), 
							.clk270(clk270), 
							.reset(reset_r), 
							.reset90(reset90_r), 
							.reset180(reset180_r), 
							.reset270(reset270_r), 
							.cq_div(cq_div_transfert_2_col1), 
							.transfer_done0(transfer_done_20), 
							.transfer_done1(transfer_done_21),