data_path.v

XILINX memory interface generator. XILINX的外部存储器接口。

wire         reset_r;
wire         reset90_r;
wire         reset180_r;
wire         reset270_r;
wire         rst_cq_div_int;
wire         rst_cq_div_reg_fd1;
wire         rst_cq_div_reg_fd2;

wire              CE_R_FB00;
wire              CE_R_FB01;
wire              CE_R_FB02;
wire              CE_R_FB03;

wire              CE_R_FB10;
wire              CE_R_FB11;
wire              CE_R_FB12;
wire              CE_R_FB13;


assign rst_cq_div_int = ~rst_cq_div;

assign read_valid_data_1 = (fifo_11_not_empty_r && fifo_11_not_empty) ? 1'b1 : 1'b0;

assign read_valid_data_2 = (fifo_13_not_empty_r && fifo_13_not_empty) ? 1'b1 : 1'b0;
                         
assign read_valid_data = read_valid_data_1 || read_valid_data_2;                         

assign u_data_val = rd_data_valid;



assign fifo_11_not_empty = (fifo_00_rd_addr[3:0] == fifo_11_wr_addr[3:0]) ? 1'b0 : 1'b1;                                                                     
assign fifo_13_not_empty = (fifo_02_rd_addr[3:0] == fifo_13_wr_addr[3:0]) ? 1'b0 : 1'b1;

// Write Address incrementation for the read FIFO
always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_00_wr_addr <= 4'h0;
    else if (transfer_done_00 == 1'b1)
      fifo_00_wr_addr <= fifo_00_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_01_wr_addr <= 4'h0;
    else if (transfer_done_01 == 1'b1) 
      fifo_01_wr_addr <= fifo_01_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_02_wr_addr <= 4'h0;
    else if (transfer_done_02 == 1'b1)
      fifo_02_wr_addr <= fifo_02_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_03_wr_addr <= 4'h0;
    else if (transfer_done_03 == 1'b1)
      fifo_03_wr_addr <= fifo_03_wr_addr + 1'b1;
end
//----------------------------------------------------------

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_10_wr_addr <= 4'h0;
    else if (transfer_done_10 == 1'b1) 
      fifo_10_wr_addr <= fifo_10_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_11_wr_addr <= 4'h0;
    else if (transfer_done_11 == 1'b1)
      fifo_11_wr_addr <= fifo_11_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_12_wr_addr <= 4'h0;
    else if (transfer_done_12 == 1'b1)
      fifo_12_wr_addr <= fifo_12_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_13_wr_addr <= 4'h0;
    else if (transfer_done_13 == 1'b1) 
      fifo_13_wr_addr <= fifo_13_wr_addr + 1'b1;
end

//---------------------------------------------------------------------------------------------------------------------

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_20_wr_addr <= 4'h0;
    else if (transfer_done_20 == 1'b1)
      fifo_20_wr_addr <= fifo_20_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_21_wr_addr <= 4'h0;
    else if (transfer_done_21 == 1'b1) 
      fifo_21_wr_addr <= fifo_21_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_22_wr_addr <= 4'h0;
    else if (transfer_done_22 == 1'b1)
      fifo_22_wr_addr <= fifo_22_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_23_wr_addr <= 4'h0;
    else if (transfer_done_23 == 1'b1)
      fifo_23_wr_addr <= fifo_23_wr_addr + 1'b1;
end

//-----------------------------------------------------------------------------------------------------------------------

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_30_wr_addr <= 4'h0;
    else if (transfer_done_30 == 1'b1)
      fifo_30_wr_addr <= fifo_30_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_31_wr_addr <= 4'h0;
    else if (transfer_done_31 == 1'b1) 
      fifo_31_wr_addr <= fifo_31_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_32_wr_addr <= 4'h0;
    else if (transfer_done_32 == 1'b1)
      fifo_32_wr_addr <= fifo_32_wr_addr + 1'b1;
end

always @ (posedge clk90)           
begin                     
    if (reset90_r == 1'b1)
      fifo_33_wr_addr <= 4'h0;
    else if (transfer_done_33 == 1'b1)
      fifo_33_wr_addr <= fifo_33_wr_addr + 1'b1;
end


// Read Address incrementation for the read FIFO and Single data rate data sequencing