write_burst_4.v

XILINX memory interface generator. XILINX的外部存储器接口。

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//**  QDR(tm)-II SRAM Virtex(tm)-II Interface                         Verilog instanciation
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// Preparation for data to be sent to the memory

`timescale 1 ns/1 ps

module write_burst_4 (CLK90, CLK270, D0, D1, 
//W_n, W_BAR, 
Q, CLK180, RESET); // RAKCHOPR

// Parameters

   parameter data_bits = 9 -1; // Size of the data bus -1

// Signals
   input CLK90;  
   input CLK270;
   input [data_bits : 0] D0; 
   input [data_bits : 0] D1; 
   input CLK180;
   input RESET; // RAKCHOPR
   
   output [data_bits : 0] Q; 

   wire [data_bits : 0] Q;
   wire [data_bits : 0] D1_S1;
   wire [data_bits : 0] D0_S1;
   wire [data_bits : 0] D0_Initial;
   wire [data_bits : 0] D1_S2;
   wire [data_bits : 0] D0_S2;
                   
//*****************************************************************************************
// Register and pipelining for written data and for write command
//*****************************************************************************************
                   
   
   FD WRT_FDC_D0_initial_[data_bits:0]  ( .Q(D0_Initial[data_bits:0]), .D(D0[data_bits:0]), .C(CLK180)); // Initial pipeline stage for data D1 and D3 for 4 word burst mode
   
   FD WRT_FDC_D1_S1_[data_bits:0]  (.Q(D1_S1[data_bits:0]),  .D(D1[data_bits:0]),  .C(CLK270)); // Data pipeline stage 1
   FD WRT_FDC_D0_S1_[data_bits:0]  (.Q(D0_S1[data_bits:0]),  .D(D0_Initial[data_bits:0]),  .C(CLK90)); // Data pipeline stage 1
   
   FD WRT_FDC_D1_S2_[data_bits:0]  (.Q(D1_S2[data_bits:0]),  .D(D1_S1[data_bits:0]),  .C(CLK270)); // Data pipeline stage 2
   FD WRT_FDC_D0_S2_[data_bits:0]  (.Q(D0_S2[data_bits:0]),  .D(D0_S1[data_bits:0]),  .C(CLK90)); // Data pipeline stage 2
   
   FDDRRSE WRT_FDDR_DQ_[data_bits:0]  (.Q(Q[data_bits:0]), .D0(D0_S2[data_bits:0]), .D1(D1_S2[data_bits:0]), .C0(CLK90), .C1(CLK270), .CE(1'b1), .R(1'b0), .S(1'b0)); // Output DDR register in DDR IOBs
endmodule