ram_18d.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 36 行

`timescale 1ns/100ps

module RAM_18D (
	         DPO,  
	         A0,   
	         A1,   
	         A2,   
	         A3,   
	         D,    
	         DPRA0,
	         DPRA1,
	         DPRA2,
	         DPRA3,
	         WCLK, 
	         WE   
                 );

parameter memory_width = 9 -1; // Size of the data bus -1
               
   input          A0;
   input          A1;
   input          A2;   
   input 	  A3;
   input 	  DPRA0; 
   input 	  DPRA1;   
   input 	  DPRA2;
   input 	  DPRA3;
   input 	  WCLK;
   input          WE;
   input [8:0]   D;

   output [8:0]  DPO;

RAM16X1D  B_[memory_width : 0] ( .D(D[memory_width : 0]), .WE(WE), .WCLK(WCLK), .A0(A0), .A1(A1), .A2(A2), .A3(A3), .DPRA0(DPRA0), .DPRA1(DPRA1), .DPRA2(DPRA2), .DPRA3(DPRA3), .SPO(open), .DPO(DPO[memory_width : 0]));                                                                                                                                                                                                                                       
                                                                                                                                                                                                                            
endmodule