📄 data_path.v
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fifo_02_wr_addr <= fifo_02_wr_addr + 1'b1;
end
always @ (posedge clk90)
begin
if (reset90_r == 1'b1)
fifo_03_wr_addr <= 4'h0;
else if (transfer_done_03 == 1'b1)
fifo_03_wr_addr <= fifo_03_wr_addr + 1'b1;
end
// Read Address incrementation for the read FIFO and Single data rate data sequencing
always @ (posedge clk90)
begin
if (reset90_r == 1'b1)
begin
next_state <= 1'b0;
fifo_00_rd_addr <= 4'h0;
fifo_02_rd_addr <= 4'h0;
user_output_data <= 18'd0;
end
else
case (next_state)
1'b0: begin
if (read_valid_data_1 == 1'b1)
begin
next_state <= 1'b1;
fifo_00_rd_addr <= fifo_00_rd_addr + 1'b1;
user_output_data <= {fifo_00_data_out,fifo_01_data_out};
end
else
next_state <= 1'b0;
end
1'b1: begin
if (read_valid_data_2 == 1'b1)
begin
next_state <= 1'b0;
fifo_02_rd_addr <= fifo_02_rd_addr + 1'b1;
user_output_data <= {fifo_02_data_out,fifo_03_data_out};
end
else
next_state <= 1'b1;
end
default: begin
next_state <= 1'b0;
fifo_00_rd_addr <= 4'h0;
fifo_02_rd_addr <= 4'h0;
user_output_data <=18'd0;
end
endcase
end
always @ (posedge clk90)
begin
if (reset90_r == 1'b1)
begin
fifo_11_not_empty_r <= 1'b0;
fifo_13_not_empty_r <= 1'b0;
rd_data_valid <= 1'b0;
end
else
begin
fifo_11_not_empty_r <= fifo_11_not_empty;
fifo_13_not_empty_r <= fifo_13_not_empty;
rd_data_valid <= read_valid_data;
end
end
/***********************************************************************
// Reset flip-flops
***********************************************************************/
FD rst0_r ( .Q(reset_r), .C(clk), .D(reset) );
FD rst90_r ( .Q(reset90_r), .C(clk90), .D(reset90) );
FD rst180_r ( .Q(reset180_r), .C(clk180), .D(reset180) );
FD rst270_r ( .Q(reset270_r), .C(clk270), .D(reset270) );
//***********************************************************************
// Read Data Capture Module Instantiations
//***********************************************************************
// CQ IOB instantiations
//***********************************************************************
v2p_qdr2_input_buffer v2p_qdr2_input_buffer0 ( .qdr2_in(qdr2_cq[0]), .read_data_in(cq_int_delay_in0));
//**************************************************************************************************
// CQ Internal Delay Circuit implemented in LUTs
//**************************************************************************************************
cq_delay cq_delay0_col0 ( .clk_in(cq_int_delay_in0), .sel_in(delay_sel), .clk_out(cq_delayed_col0)); // Internal Clock Delay circuit placed in the first column (for falling edge data) adjacent to IOBs
cq_delay cq_delay0_col1 ( .clk_in(cq_int_delay_in0), .sel_in(delay_sel), .clk_out(cq_delayed_col1)); // Internal Clock Delay circuit placed in the second column (for rising edge data) adjacent to IOBs
//***************************************************************************************************
// CQ Divide by 2 instantiations
//***************************************************************************************************
FD FD_R_n_0 (.Q(rst_cq_div_reg_fd1), .C(cq_delayed_col1), .D(rst_cq_div));
qdr2_cq_div qdr2_cq_div0 ( .cq(cq_delayed_col0),
.cq1(cq_delayed_col1),
.rst_cq_div(rst_cq_div_reg_fd1),
.cq_tranfert_col1(cq_div_transfert_0_col0),
.cq_tranfert_col0(cq_div_transfert_0_col1));
//****************************************************************************************************************
// Transfer done instantiations (One instantiation per strobe)
//****************************************************************************************************************
qdr2_transfer_done qdr2_transfer_done0 ( .clk0(clk),
.clk90(clk90),
.clk180(clk180),
.clk270(clk270),
.reset(reset_r),
.reset90(reset90_r),
.reset180(reset180_r),
.reset270(reset270_r),
.cq_div(cq_div_transfert_0_col1),
.transfer_done0(transfer_done_00),
.transfer_done1(transfer_done_01),
.transfer_done2(transfer_done_02),
.transfer_done3(transfer_done_03));
//****************************************************************************************************************
// Generation of the synchronous CE for the data capture FD.
//****************************************************************************************************************
FD FD_R_n_0_DC (.Q(CE_R_FB0),
.C(cq_delayed_col1), //changed col1 to col0
.D(rst_cq_div));
FD FD_R_n_1_DC (.Q(CE_R_FB1),
.C(~cq_delayed_col0),
.D(CE_R_FB0));
FD FD_R_n_2_DC (.Q(CE_R_FB2),
.C(cq_delayed_col1), //changed col1 to col0
.D(CE_R_FB0));
FD FD_R_n_3_DC (.Q(CE_R_FB3),
.C(~cq_delayed_col0),
.D(CE_R_FB1));
//******************************************************************************************************************************
// Q Data bits instantiations (36-bits)
//******************************************************************************************************************************
qdr2_qbit_cq qdr2_qbit_0 ( .reset(reset270_r), .cq(cq_delayed_col0), .cq1(cq_delayed_col1), .qdr2_q(qdr2_q[0] ), .CE_R_FB0(CE_R_FB0), .CE_R_FB1(CE_R_FB1), .CE_R_FB2(CE_R_FB2), .CE_R_FB3(CE_R_FB3), .fbit_0(fbit_0[0] ), .fbit_1(fbit_1[0] ), .fbit_2(fbit_2[0] ), .fbit_3(fbit_3[0] ));
qdr2_qbit_cq qdr2_qbit_1 ( .reset(reset270_r), .cq(cq_delayed_col0), .cq1(cq_delayed_col1), .qdr2_q(qdr2_q[1] ), .CE_R_FB0(CE_R_FB0), .CE_R_FB1(CE_R_FB1), .CE_R_FB2(CE_R_FB2), .CE_R_FB3(CE_R_FB3), .fbit_0(fbit_0[1] ), .fbit_1(fbit_1[1] ), .fbit_2(fbit_2[1] ), .fbit_3(fbit_3[1] ));
qdr2_qbit_cq qdr2_qbit_2 ( .reset(reset270_r), .cq(cq_delayed_col0), .cq1(cq_delayed_col1), .qdr2_q(qdr2_q[2] ), .CE_R_FB0(CE_R_FB0), .CE_R_FB1(CE_R_FB1), .CE_R_FB2(CE_R_FB2), .CE_R_FB3(CE_R_FB3), .fbit_0(fbit_0[2] ), .fbit_1(fbit_1[2] ), .fbit_2(fbit_2[2] ), .fbit_3(fbit_3[2] ));
qdr2_qbit_cq qdr2_qbit_3 ( .reset(reset270_r), .cq(cq_delayed_col0), .cq1(cq_delayed_col1), .qdr2_q(qdr2_q[3] ), .CE_R_FB0(CE_R_FB0), .CE_R_FB1(CE_R_FB1), .CE_R_FB2(CE_R_FB2), .CE_R_FB3(CE_R_FB3), .fbit_0(fbit_0[3] ), .fbit_1(fbit_1[3] ), .fbit_2(fbit_2[3] ), .fbit_3(fbit_3[3] ));
qdr2_qbit_cq qdr2_qbit_4 ( .reset(reset270_r), .cq(cq_delayed_col0), .cq1(cq_delayed_col1), .qdr2_q(qdr2_q[4] ), .CE_R_FB0(CE_R_FB0), .CE_R_FB1(CE_R_FB1), .CE_R_FB2(CE_R_FB2), .CE_R_FB3(CE_R_FB3), .fbit_0(fbit_0[4] ), .fbit_1(fbit_1[4] ), .fbit_2(fbit_2[4] ), .fbit_3(fbit_3[4] ));
qdr2_qbit_cq qdr2_qbit_5 ( .reset(reset270_r), .cq(cq_delayed_col0), .cq1(cq_delayed_col1), .qdr2_q(qdr2_q[5] ), .CE_R_FB0(CE_R_FB0), .CE_R_FB1(CE_R_FB1), .CE_R_FB2(CE_R_FB2), .CE_R_FB3(CE_R_FB3), .fbit_0(fbit_0[5] ), .fbit_1(fbit_1[5] ), .fbit_2(fbit_2[5] ), .fbit_3(fbit_3[5] ));
qdr2_qbit_cq qdr2_qbit_6 ( .reset(reset270_r), .cq(cq_delayed_col0), .cq1(cq_delayed_col1), .qdr2_q(qdr2_q[6] ), .CE_R_FB0(CE_R_FB0), .CE_R_FB1(CE_R_FB1), .CE_R_FB2(CE_R_FB2), .CE_R_FB3(CE_R_FB3), .fbit_0(fbit_0[6] ), .fbit_1(fbit_1[6] ), .fbit_2(fbit_2[6] ), .fbit_3(fbit_3[6] ));
qdr2_qbit_cq qdr2_qbit_7 ( .reset(reset270_r), .cq(cq_delayed_col0), .cq1(cq_delayed_col1), .qdr2_q(qdr2_q[7] ), .CE_R_FB0(CE_R_FB0), .CE_R_FB1(CE_R_FB1), .CE_R_FB2(CE_R_FB2), .CE_R_FB3(CE_R_FB3), .fbit_0(fbit_0[7] ), .fbit_1(fbit_1[7] ), .fbit_2(fbit_2[7] ), .fbit_3(fbit_3[7] ));
qdr2_qbit_cq qdr2_qbit_8 ( .reset(reset270_r), .cq(cq_delayed_col0), .cq1(cq_delayed_col1), .qdr2_q(qdr2_q[8] ), .CE_R_FB0(CE_R_FB0), .CE_R_FB1(CE_R_FB1), .CE_R_FB2(CE_R_FB2), .CE_R_FB3(CE_R_FB3), .fbit_0(fbit_0[8] ), .fbit_1(fbit_1[8] ), .fbit_2(fbit_2[8] ), .fbit_3(fbit_3[8] ));
//*************************************************************************************************************************
// Distributed RAM 18 bits wide FIFO instantiations (4 FIFOs per strobe, 1 for each fbit0 through 3)
//*************************************************************************************************************************
// FIFOs associated with qdr2_cq(0)
RAM_18D RAM_18D_cq0_fbit0 ( .DPO(fifo_00_data_out), .A0(fifo_00_wr_addr[0]), .A1(fifo_00_wr_addr[1]), .A2(fifo_00_wr_addr[2]), .A3(fifo_00_wr_addr[3]), .D(fbit_0[8:0]), .DPRA0(fifo_00_rd_addr[0]), .DPRA1(fifo_00_rd_addr[1]), .DPRA2(fifo_00_rd_addr[2]), .DPRA3(fifo_00_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_00));
RAM_18D RAM_18D_cq0_fbit1 ( .DPO(fifo_01_data_out), .A0(fifo_01_wr_addr[0]), .A1(fifo_01_wr_addr[1]), .A2(fifo_01_wr_addr[2]), .A3(fifo_01_wr_addr[3]), .D(fbit_1[8:0]), .DPRA0(fifo_00_rd_addr[0]), .DPRA1(fifo_00_rd_addr[1]), .DPRA2(fifo_00_rd_addr[2]), .DPRA3(fifo_00_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_01));
RAM_18D RAM_18D_cq0_fbit2 ( .DPO(fifo_02_data_out), .A0(fifo_02_wr_addr[0]), .A1(fifo_02_wr_addr[1]), .A2(fifo_02_wr_addr[2]), .A3(fifo_02_wr_addr[3]), .D(fbit_2[8:0]), .DPRA0(fifo_02_rd_addr[0]), .DPRA1(fifo_02_rd_addr[1]), .DPRA2(fifo_02_rd_addr[2]), .DPRA3(fifo_02_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_02));
RAM_18D RAM_18D_cq0_fbit3 ( .DPO(fifo_03_data_out), .A0(fifo_03_wr_addr[0]), .A1(fifo_03_wr_addr[1]), .A2(fifo_03_wr_addr[2]), .A3(fifo_03_wr_addr[3]), .D(fbit_3[8:0]), .DPRA0(fifo_02_rd_addr[0]), .DPRA1(fifo_02_rd_addr[1]), .DPRA2(fifo_02_rd_addr[2]), .DPRA3(fifo_02_rd_addr[3]), .WCLK(clk90), .WE(transfer_done_03));
endmodule
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