2vp7ff672.txt

XILINX memory interface generator. XILINX的外部存储器接口。

############################################################################
# Calibration Circuit Constraints
############################################################################

INST "%sinfrastructure_top0/cal_top0/cal_dcm" LOC="DCM_X0Y0";

INST "%sinfrastructure_top0/cal_top0" AREA_GROUP=gp1;
AREA_GROUP "gp1" RANGE = SLICE_X0Y0:SLICE_X23Y15;


INST "%sinfrastructure_top0/cal_top0/cal_clkd2" LOC = SLICE_X0Y0;
INST "%sinfrastructure_top0/cal_top0/cal_phClkd2" LOC = SLICE_X0Y3;

INST "%sinfrastructure_top0/cal_top0/hxSampReg0" LOC = SLICE_X2Y0;

INST "%sinfrastructure_top0/cal_top0/cal_suClkd2" LOC = SLICE_X0Y4;
INST "%sinfrastructure_top0/cal_top0/cal_suPhClkd2" LOC = SLICE_X2Y5;
INST "%sinfrastructure_top0/cal_top0/phSampReg0" LOC = SLICE_X2Y4;
#############################################################
# LUT Location Constraints for dqs_delay Circuit
#############################################################
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/one" LOC = SLICE_X2Y2; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/one" BEL = F; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/two" LOC = SLICE_X2Y3; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/two" BEL = F; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/three" LOC = SLICE_X2Y3; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/three" BEL = G; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/four" LOC = SLICE_X3Y2; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/four" BEL = F; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/five" LOC = SLICE_X3Y2; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/five" BEL = G; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/six" LOC = SLICE_X3Y3; 
 INST "%sinfrastructure_top0/cal_top0/ckt_to_cal/six" BEL = G; 


###no_dcm
############################################################################
#DCM, MACRO and BUFG  Constraints
############################################################################

INST "%sinfrastructure_top0/clk_dcm0/DCM_INST1" LOC="DCM_X1Y0";

INST "%sinfrastructure_top0/clk_dcm0/BUFG_CLK0/u1" LOC="BUFGMUX6P";
INST "%sinfrastructure_top0/clk_dcm0/BUFG_CLK90/u1" LOC="BUFGMUX7S";


NET "%sinfrastructure_top0/cal_top0/clkdiv2" MAXDELAY = 600 ps;
NET "%sinfrastructure_top0/cal_top0/phclkdiv2" MAXDELAY = 600 ps;

NET "%sinfrastructure_top0/cal_top0/suclkdiv2" MAXDELAY = 600ps;
NET "%sinfrastructure_top0/cal_top0/suphclkdiv2" MAXDELAY = 700ps;


##############################################################################
# MaxDelay constraints                                                                                                #
##############################################################################

NET "%sinfrastructure_top0/clk_dcm0/clk0dcm" MAXDELAY = 0.450ns;
NET "%sinfrastructure_top0/clk_dcm0/clk90dcm" MAXDELAY = 0.450ns;
NET "%sinfrastructure_top0/clk_dcm0/clk0d2inv" MAXDELAY = 0.755ns;
NET "%sinfrastructure_top0/clk_dcm0/clk90d2inv" MAXDELAY = 0.755ns;