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📄 mem_interface_top.ucf

📁 XILINX memory interface generator. XILINX的外部存储器接口。
💻 UCF
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INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
#############################################################
##  constraints for bit ddr2_dq, 11
NET  "cntrl0_ddr2_dq(11)" LOC = AB26;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
#############################################################
##  constraints for bit ddr2_dqs, 1
NET  "cntrl0_ddr2_dqs(1)" LOC = AB27;
NET "*/ddr2_top0/dqs_int_delay_in1"
 ROUTE="{2;1;-7!-1;-93904;-86760;22;0;14;16;8!0;-159;0;38!1;2479;-1269;2!"
 "2;4457;1453;0!2;0;-400!2;0;80!2;-25;-83!2;-40;80!2;96;-400!2;-3512;320!2;"
 "-40;80!2;65;-77!2;0;80!2;0;320!2;31;-723!3;3752;723;4;6;15;18;13!4;0;"
 "-400;4;6;14;13!5;0;80;4;6;14;21!6;-160;-448;4;6;13;10!7;0;80;4;6;13;18!8;"
 "0;-400;4;6;12;13!9;-3456;320;4;3;13;10!10;0;80;4;3;13;18!11;160;288;4;3;"
 "14;13!12;0;80;4;3;14;21!13;0;320;4;3;15;18!14;-160;-1088;4;3;12;13!}";
## LUT location constraints for col 0
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/one" LOC = SLICE_X2Y20;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/one" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/two" LOC = SLICE_X2Y21;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/two" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/three" LOC = SLICE_X2Y21;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/three" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/four" LOC = SLICE_X3Y20;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/four" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/five" LOC = SLICE_X3Y20;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/five" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/six" LOC = SLICE_X3Y21;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col0/six" BEL = G;

## LUT location constraints for col 1
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/one" LOC = SLICE_X0Y20;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/one" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/two" LOC = SLICE_X0Y21;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/two" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/three" LOC = SLICE_X0Y21;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/three" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/four" LOC = SLICE_X1Y20;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/four" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/five" LOC = SLICE_X1Y20;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/five" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/six" LOC = SLICE_X1Y21;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay1_col1/six" BEL = G;
#############################################################
##  constraints for bit ddr2_dqs_n, 1
NET  "cntrl0_ddr2_dqs_n(1)" LOC = AB28;
#############################################################
##  constraints for bit ddr2_dq, 12
NET  "cntrl0_ddr2_dq(12)" LOC = AE34;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit0" RLOC_ORIGIN = X0Y22;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/dq";
#############################################################
##  constraints for bit ddr2_dq, 13
NET  "cntrl0_ddr2_dq(13)" LOC = AD34;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit13/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit12/dq";
#############################################################
##  constraints for bit ddr2_dq, 14
NET  "cntrl0_ddr2_dq(14)" LOC = AA25;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit0" RLOC_ORIGIN = X0Y24;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/dq";
#############################################################
##  constraints for bit ddr2_dq, 15
NET  "cntrl0_ddr2_dq(15)" LOC = AA26;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit15/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit14/dq";
#############################################################
##  constraints for bit ddr2_dq, 16
NET  "cntrl0_ddr2_dq(16)" LOC = AB29;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit0" RLOC_ORIGIN = X0Y28;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit0" RLOC = X0Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit2" RLOC = X1Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit1" RLOC = X3Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit3" RLOC = X2Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
#############################################################
##  constraints for bit ddr2_dq, 17
NET  "cntrl0_ddr2_dq(17)" LOC = AB30;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit0" RLOC = X0Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit2" RLOC = X1Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit1" RLOC = X3Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit3" RLOC = X2Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit17/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
#############################################################
##  constraints for bit ddr2_dq, 18
NET  "cntrl0_ddr2_dq(18)" LOC = AA27;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit18/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
#############################################################
##  constraints for bit ddr2_dq, 19
NET  "cntrl0_ddr2_dq(19)" LOC = AA28;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit19/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit16/dq";
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