mem_interface_top.ucf

XILINX memory interface generator. XILINX的外部存储器接口。

INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit20/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit20/dq";
#############################################################
##  constraints for bit ddr2_dq, 21
NET  "cntrl0_ddr2_dq(21)" LOC = AB32;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit20/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit20/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit20/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit21/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit20/dq";
#############################################################
##  constraints for bit ddr2_dqs, 2
NET  "cntrl0_ddr2_dqs(2)" LOC = Y25;
## LUT location constraints for col 0
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/one" LOC = SLICE_X2Y32;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/one" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/two" LOC = SLICE_X2Y33;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/two" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/three" LOC = SLICE_X2Y33;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/three" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/four" LOC = SLICE_X3Y32;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/four" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/five" LOC = SLICE_X3Y32;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/five" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/six" LOC = SLICE_X3Y33;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col0/six" BEL = G;

## LUT location constraints for col 1
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/one" LOC = SLICE_X0Y32;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/one" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/two" LOC = SLICE_X0Y33;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/two" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/three" LOC = SLICE_X0Y33;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/three" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/four" LOC = SLICE_X1Y32;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/four" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/five" LOC = SLICE_X1Y32;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/five" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/six" LOC = SLICE_X1Y33;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay2_col1/six" BEL = G;
#############################################################
##  constraints for bit no_dpin, 2
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div2/col0" LOC = SLICE_X3Y35;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div2/col1" LOC = SLICE_X1Y35;
NET "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div2/dqs_divn" MAXDELAY = 1200ps;
NET "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div2/dqs_divp" MAXDELAY = 1200ps;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_clk0" LOC = SLICE_X1Y34;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_clk0" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_clk90" LOC = SLICE_X3Y34;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_clk90" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_rst90" LOC = SLICE_X3Y34;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_rst90" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_clk180" LOC = SLICE_X0Y35;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_clk180" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_clk270" LOC = SLICE_X2Y35;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_clk270" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_rst270" LOC = SLICE_X2Y35;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0_rst270" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0" LOC = SLICE_X2Y35;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone0" BEL = F;

INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone1_clk270" LOC = SLICE_X5Y35;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone1_clk270" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone2_clk270" LOC = SLICE_X5Y35;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone2_clk270" BEL = FFY;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone1_clk90" LOC = SLICE_X5Y34;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone1_clk90" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone2_clk90" LOC = SLICE_X5Y34;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone2_clk90" BEL = FFY;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone1" LOC = SLICE_X5Y34;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone1" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone2" LOC = SLICE_X5Y34;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone2" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone3_clk90" LOC = SLICE_X4Y35;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone3_clk90" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone3_clk270" LOC = SLICE_X4Y34;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone3_clk270" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone3" LOC = SLICE_X4Y34;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done2/xdone3" BEL = F;
#############################################################
##  constraints for bit ddr2_dq, 22
NET  "cntrl0_ddr2_dq(22)" LOC = W25;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit0" RLOC_ORIGIN = X0Y36;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/dq";
#############################################################
##  constraints for bit ddr2_dq, 23
NET  "cntrl0_ddr2_dq(23)" LOC = W26;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit23/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit22/dq";
#############################################################
##  constraints for bit ddr2_dq, 24
NET  "cntrl0_ddr2_dq(24)" LOC = AB33;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit0" RLOC_ORIGIN = X0Y38;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/dq";
#############################################################
##  constraints for bit ddr2_dq, 25
NET  "cntrl0_ddr2_dq(25)" LOC = AA33;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit25/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit24/dq";
#############################################################
##  constraints for bit ddr2_dqs, 3
NET  "cntrl0_ddr2_dqs(3)" LOC = W27;
## LUT location constraints for col 0
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/one" LOC = SLICE_X2Y40;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/one" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/two" LOC = SLICE_X2Y41;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/two" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/three" LOC = SLICE_X2Y41;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/three" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/four" LOC = SLICE_X3Y40;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/four" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/five" LOC = SLICE_X3Y40;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/five" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/six" LOC = SLICE_X3Y41;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col0/six" BEL = G;

## LUT location constraints for col 1
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col1/one" LOC = SLICE_X0Y40;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col1/one" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col1/two" LOC = SLICE_X0Y41;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col1/two" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col1/three" LOC = SLICE_X0Y41;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col1/three" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col1/four" LOC = SLICE_X1Y40;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay3_col1/four" BEL = F;
INST "*/ddr2_top0/data_path0/data_