📄 mem_interface_top.ucf
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INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/dq";
#############################################################
## constraints for bit ddr2_dq, 5
INST "cntrl0_ddr2_dq(5)" LOC = AF31;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit0" RLOC_ORIGIN = X0Y8;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit0" RLOC = X0Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit2" RLOC = X1Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit1" RLOC = X3Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit3" RLOC = X2Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
#############################################################
## constraints for bit ddr2_dq, 6
INST "cntrl0_ddr2_dq(6)" LOC = AF32;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit0" RLOC = X0Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit2" RLOC = X1Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit1" RLOC = X3Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit3" RLOC = X2Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit6/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
#############################################################
## constraints for bit ddr2_dq, 7
INST "cntrl0_ddr2_dq(7)" LOC = AC25;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit7/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit5/dq";
#############################################################
## constraints for bit no_dpin, 0
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div0/col0" LOC = SLICE_X3Y11;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div0/col1" LOC = SLICE_X1Y11;
NET "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div0/dqs_divn" MAXDELAY = 1200ps;
NET "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div0/dqs_divp" MAXDELAY = 1200ps;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_clk0" LOC = SLICE_X1Y10;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_clk0" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_clk90" LOC = SLICE_X3Y10;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_clk90" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_rst90" LOC = SLICE_X3Y10;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_rst90" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_clk180" LOC = SLICE_X0Y11;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_clk180" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_clk270" LOC = SLICE_X2Y11;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_clk270" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_rst270" LOC = SLICE_X2Y11;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0_rst270" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0" LOC = SLICE_X2Y11;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone0" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone1_clk270" LOC = SLICE_X5Y11;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone1_clk270" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone2_clk270" LOC = SLICE_X5Y11;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone2_clk270" BEL = FFY;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone1_clk90" LOC = SLICE_X5Y10;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone1_clk90" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone2_clk90" LOC = SLICE_X5Y10;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone2_clk90" BEL = FFY;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone1" LOC = SLICE_X5Y10;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone1" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone2" LOC = SLICE_X5Y10;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone2" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone3_clk90" LOC = SLICE_X4Y11;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone3_clk90" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone3_clk270" LOC = SLICE_X4Y10;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone3_clk270" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone3" LOC = SLICE_X4Y10;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done0/xdone3" BEL = F;
#############################################################
## constraints for bit no_dpin, 1
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div1/col0" LOC = SLICE_X3Y15;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div1/col1" LOC = SLICE_X1Y15;
NET "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div1/dqs_divn" MAXDELAY = 1200ps;
NET "*/ddr2_top0/data_path0/data_read_controller0/ddr2_dqs_div1/dqs_divp" MAXDELAY = 1200ps;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_clk0" LOC = SLICE_X1Y14;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_clk0" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_clk90" LOC = SLICE_X3Y14;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_clk90" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_rst90" LOC = SLICE_X3Y14;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_rst90" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_clk180" LOC = SLICE_X0Y15;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_clk180" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_clk270" LOC = SLICE_X2Y15;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_clk270" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_rst270" LOC = SLICE_X2Y15;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0_rst270" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0" LOC = SLICE_X2Y15;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone0" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone1_clk270" LOC = SLICE_X5Y15;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone1_clk270" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone2_clk270" LOC = SLICE_X5Y15;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone2_clk270" BEL = FFY;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone1_clk90" LOC = SLICE_X5Y14;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone1_clk90" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone2_clk90" LOC = SLICE_X5Y14;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone2_clk90" BEL = FFY;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone1" LOC = SLICE_X5Y14;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone1" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone2" LOC = SLICE_X5Y14;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone2" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone3_clk90" LOC = SLICE_X4Y15;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone3_clk90" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone3_clk270" LOC = SLICE_X4Y14;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone3_clk270" BEL = FFX;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone3" LOC = SLICE_X4Y14;
INST "*/ddr2_top0/data_path0/data_read_controller0/ddr2_transfer_done1/xdone3" BEL = F;
#############################################################
## constraints for bit ddr2_dq, 8
INST "cntrl0_ddr2_dq(8)" LOC = AD29;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit0" RLOC_ORIGIN = X0Y16;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit0" RLOC = X0Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit2" RLOC = X1Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit1" RLOC = X3Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit3" RLOC = X2Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
#############################################################
## constraints for bit ddr2_dq, 9
INST "cntrl0_ddr2_dq(9)" LOC = AD30;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit0" RLOC = X0Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit2" RLOC = X1Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit1" RLOC = X3Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit3" RLOC = X2Y1;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit9/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
#############################################################
## constraints for bit ddr2_dq, 10
INST "cntrl0_ddr2_dq(10)" LOC = AB25;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit10/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit8/dq";
#############################################################
## constraints for bit ddr2_dq, 11
INST "cntrl0_ddr2_dq(11)" LOC = AB26;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit11/fbit0" BEL = "FFX";
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