📄 mem_interface_top.ucf
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NET "cntrl0_ddr2_clk1b" LOC = "V26" ;
NET "cntrl0_ddr2_clk2" LOC = "T32" ;
NET "cntrl0_ddr2_clk2b" LOC = "T31" ;
NET "cntrl0_ddr2_clk3" LOC = "L34" ;
NET "cntrl0_ddr2_clk3b" LOC = "K34" ;
NET "cntrl0_ddr2_clk4" LOC = "F31" ;
NET "cntrl0_ddr2_clk4b" LOC = "F30" ;
NET "cntrl0_ddr2_dm(0)" LOC = "AC26" ;
NET "cntrl0_ddr2_dm(1)" LOC = "AD31" ;
NET "cntrl0_ddr2_dm(2)" LOC = "AC34" ;
NET "cntrl0_ddr2_dm(3)" LOC = "Y31" ;
NET "cntrl0_ddr2_dm(4)" LOC = "U27" ;
NET "cntrl0_ddr2_dm(5)" LOC = "R28" ;
NET "cntrl0_ddr2_dm(6)" LOC = "N32" ;
NET "cntrl0_ddr2_dm(7)" LOC = "M28" ;
NET "cntrl0_ddr2_dm(8)" LOC = "J28" ;
NET "cntrl0_ddr2_ODT0" LOC = "AG33" ;
NET "cntrl0_ddr2_rasb" LOC = "AE30" ;
NET "cntrl0_ddr2_casb" LOC = "AE31" ;
NET "cntrl0_ddr2_web" LOC = "AF33" ;
NET "cntrl0_ddr2_cke" LOC = "AE33" ;
NET "cntrl0_ddr2_ba(0)" LOC = "AC31" ;
NET "cntrl0_ddr2_ba(1)" LOC = "AC32" ;
NET "cntrl0_ddr2_csb" LOC = "AD33" ;
#NET "cntrl0_" LOC = "W31" ;
NET "cntrl0_ddr2_address(12)" LOC = "V33" ;
NET "cntrl0_ddr2_address(10)" LOC = "T26" ;
NET "cntrl0_ddr2_address(11)" LOC = "T25" ;
NET "cntrl0_ddr2_address(8)" LOC = "R26" ;
NET "cntrl0_ddr2_address(9)" LOC = "R25" ;
NET "cntrl0_ddr2_address(6)" LOC = "P26" ;
NET "cntrl0_ddr2_address(7)" LOC = "P25" ;
#NET "cntrl0_" LOC = "N26" ;
NET "cntrl0_ddr2_address(4)" LOC = "M26" ;
NET "cntrl0_ddr2_address(5)" LOC = "M25" ;
NET "cntrl0_ddr2_address(2)" LOC = "E32" ;
NET "cntrl0_ddr2_address(3)" LOC = "E31" ;
NET "cntrl0_ddr2_address(0)" LOC = "F28" ;
NET "cntrl0_ddr2_address(1)" LOC = "F27" ;
NET "cntrl0_led_error_output1" LOC = "AE15" ;
NET "reset_in" LOC = "AH22" ;
#########################################################################
# MAXDELAY constraints #
#########################################################################
NET "*/ddr2_top0/data_path0/data_read0/fbit_0(*)" MAXDELAY = 1200ps;
NET "*/ddr2_top0/data_path0/data_read0/fbit_1(*)" MAXDELAY = 1200ps;
NET "*/ddr2_top0/data_path0/data_read0/fbit_2(*)" MAXDELAY = 1200ps;
NET "*/ddr2_top0/data_path0/data_read0/fbit_3(*)" MAXDELAY = 1200ps;
NET "*/ddr2_top0/controller0/rst_dqs_div_int" MAXDELAY = 600ps ;
NET "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delayed" MAXDELAY = 1500ps;
NET "*/ddr2_top0/data_path0/data_read_controller0/fifo_*_wr_addr*" MAXDELAY = 3000ps;
NET "*/ddr2_top0/data_path0/data_read0/fifo_*_rd_addr*" MAXDELAY = 3000ps;
NET "*/ddr2_top0/data_path0/data_read_controller0/transfer_done_*" MAXDELAY = 1500ps;
#########################################################################
########################################################################
NET "cntrl0_rst_dqs_div_in" LOC = "U29";
NET "cntrl0_rst_dqs_div_out" LOC = "U30";
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/one" LOC = SLICE_X0Y60;
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/one" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/two" LOC = SLICE_X0Y61;
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/two" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/three" LOC = SLICE_X0Y61;
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/three" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/four" LOC = SLICE_X1Y60;
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/four" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/five" LOC = SLICE_X1Y60;
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/five" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/six" LOC = SLICE_X1Y61;
INST "*/ddr2_top0/data_path0/data_read_controller0/rst_dqs_div_delay0/six" BEL = G;
#############################################################
## constraints for bit ddr2_dq, 0
INST "cntrl0_ddr2_dq(0)" LOC = AJ27;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit0" RLOC_ORIGIN = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/dq";
#############################################################
## constraints for bit ddr2_dq, 1
INST "cntrl0_ddr2_dq(1)" LOC = AJ28;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit3" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit1/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit0/dq";
#############################################################
## constraints for bit ddr2_dq, 2
INST "cntrl0_ddr2_dq(2)" LOC = AK31;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit0" RLOC_ORIGIN = X0Y2;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit2/dq";
#############################################################
## constraints for bit ddr2_dqs, 0
INST "cntrl0_ddr2_dqs(0)" LOC = AH27;
## LUT location constraints for col 0
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" LOC = SLICE_X2Y4;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/one" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" LOC = SLICE_X2Y5;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/two" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" LOC = SLICE_X2Y5;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/three" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" LOC = SLICE_X3Y4;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/four" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" LOC = SLICE_X3Y4;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/five" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" LOC = SLICE_X3Y5;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col0/six" BEL = G;
## LUT location constraints for col 1
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" LOC = SLICE_X0Y4;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/one" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" LOC = SLICE_X0Y5;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/two" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" LOC = SLICE_X0Y5;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/three" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" LOC = SLICE_X1Y4;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/four" BEL = F;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" LOC = SLICE_X1Y4;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/five" BEL = G;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" LOC = SLICE_X1Y5;
INST "*/ddr2_top0/data_path0/data_read_controller0/dqs_delay0_col1/six" BEL = G;
#############################################################
## constraints for bit ddr2_dq, 3
INST "cntrl0_ddr2_dq(3)" LOC = AL33;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit0" RLOC_ORIGIN = X0Y6;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit0" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit2" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit1" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit3" RLOC = X2Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit3" BEL = "FFY";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/fbit3" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/dq";
#############################################################
## constraints for bit ddr2_dq, 4
INST "cntrl0_ddr2_dq(4)" LOC = AL34;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit0" RLOC = X0Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit0" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit0" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit2" RLOC = X1Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit2" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit2" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/dq";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit1" RLOC = X3Y0;
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit1" BEL = "FFX";
INST "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit4/fbit1" U_SET = "*/ddr2_top0/data_path0/data_read0/ddr2_dqbit3/dq";
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