addr_gen.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.param_file.all;
--
-- pragma translate_off
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
-- pragma translate_on
--

entity addr_gen is
port(
   clk            : in std_logic;
   rst            : in std_logic;
   addr_rst       : in std_logic;
   addr_inc       : in std_logic;
   addr_out       : out std_logic_vector(((row_address_p + column_address_p + bank_address_p)- 1) downto 0);
   test_cnt_ena   : in std_logic;
   test_out       : out std_logic_vector(4 downto 0);
   burst_done     : out std_logic;
   cnt_roll       : out std_logic);
end addr_gen;


architecture arc_addr_gen of addr_gen is

attribute syn_keep : boolean;  -- Using Syn_Keep Derictive

signal addr_int 			: std_logic_vector(22 downto 0);
signal test_cnt 			: std_logic_vector(4 downto 0);
signal testcnt_reg 		: std_logic_vector(3 downto 0);

signal column_counter 	: std_logic_vector(7 downto 0);
signal ba_count       	: std_logic_vector((bank_address_p - 1) downto 0);
signal cnt            	: std_logic_vector(1 downto 0);
signal burst_done_reg   : std_logic;
signal burst_done_1_reg : std_logic;
signal cnt_roll_p     	: std_logic;
signal cnt_roll_p2    	:std_logic;

signal low            	: std_logic_vector(13 downto 0);

attribute syn_keep of low : signal is true; 

begin

low <= "00000000000000";
burst_done <=     burst_done_1_reg;

ba_count       <= (low((bank_address_p-2) downto 0) & '0'); 
addr_out <= (low(row_address_p-3 downto 0) & "10" & (low(column_address_p-9 downto 0)) & column_counter & ba_count);


process(clk)
begin
  if clk'event and clk = '1' then
     if (rst = '1' or addr_rst = '1') then
        column_counter <= "00000000";
        cnt <= "00";
      elsif addr_inc = '1' then
       
       		if cnt = "01" then 
            			cnt <= "00";
        		else
            			cnt <= cnt + "01";
        		end if;
        
        		if test_cnt_ena = '1' and cnt = "01" then 
        
          			 if column_counter = "00010000" then  --11110000
        
                 				column_counter <= "00000000";
           			else 
                				column_counter <= column_counter + "00000100";
            			end if;     
          		else 
             			column_counter <= column_counter;
        		end if;
        
     end if;
    end if;
end process;

process(clk)
begin
if(clk'event and clk = '1') then
  burst_done_reg <= ( not(rst) and column_counter(4));
end if;
end process;

process(clk)
begin
 if(clk'event and clk = '1') then
    burst_done_1_reg <= ( not(rst) and burst_done_reg);
 end if;
end process;

burst_done <= burst_done_1_reg;

process(clk)
begin
 if(clk'event and clk = '1') then
     cnt_roll_p <= not(rst) and column_counter(3) and column_counter(2) and not(column_counter(1)) and not(column_counter(0)) ;
 end if;
end process;


process(clk)
begin
 if clk'event and clk = '1' then
  if rst = '1' then
     cnt_roll_p2 <= '0';
     cnt_roll    <= '0';
  else
     cnt_roll_p2  <= cnt_roll_p;
     cnt_roll <= cnt_roll_p2;
  end if;
 end if;
end process;




--  TO TEST SINGLE BUSRT 

--process (clk)
--begin
-- if clk'event and clk = '1' then
--  if rst = '1' then
--     cnt_roll_p <= '0';
--  elsif(addr_inc = '1') then
--       cnt_roll <= '1';
--  else
--      cnt_roll <= '0';
--  end if;
--  end if;    
--end process;

--process (clk)
--begin
-- if clk'event and clk = '1' then
--  if rst = '1' then
--     burst_done_reg   <= '0';
--     burst_done_1_reg <= '0';
--     column_counter <= "00000100";
--   elsif (addr_inc = '1') then
--     burst_done_reg <= '1';
--     burst_done_1_reg <= burst_done_reg;
--  else
--     burst_done_reg <= '0';
--     burst_done_1_reg <= burst_done_reg;
-- end if;
-- end if;
--end process;




end arc_addr_gen;