virtex2.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

 );
end component;
attribute syn_black_box of IOBUF_LVDCI_15 : component is true;
component IOBUF_LVDCI_18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_18 : component is true;
component IOBUF_LVDCI_25
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_25 : component is true;
component IOBUF_LVDCI_33
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_33 : component is true;
component IOBUF_LVDCI_DV2_15
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_15 : component is true;
component IOBUF_LVDCI_DV2_18
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_18 : component is true;
component IOBUF_LVDCI_DV2_25
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_25 : component is true;
component IOBUF_LVDCI_DV2_33
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVDCI_DV2_33 : component is true;
component IOBUF_LVTTL
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL : component is true;
component IOBUF_LVTTL_F_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_12 : component is true;
component IOBUF_LVTTL_F_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_16 : component is true;
component IOBUF_LVTTL_F_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_2 : component is true;
component IOBUF_LVTTL_F_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_24 : component is true;
component IOBUF_LVTTL_F_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_4 : component is true;
component IOBUF_LVTTL_F_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_6 : component is true;
component IOBUF_LVTTL_F_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_F_8 : component is true;
component IOBUF_LVTTL_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_12 : component is true;
component IOBUF_LVTTL_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_16 : component is true;
component IOBUF_LVTTL_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_2 : component is true;
component IOBUF_LVTTL_S_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_24 : component is true;
component IOBUF_LVTTL_S_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_4 : component is true;
component IOBUF_LVTTL_S_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_6 : component is true;
component IOBUF_LVTTL_S_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_LVTTL_S_8 : component is true;
component IOBUF_PCI33_3
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_PCI33_3 : component is true;
component IOBUF_PCI66_3
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_PCI66_3 : component is true;
component IOBUF_PCIX
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_PCIX : component is true;
component IOBUF_SSTL2_I
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL2_I : component is true;
component IOBUF_SSTL2_II
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL2_II : component is true;
component IOBUF_SSTL2_II_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL2_II_DCI : component is true;
component IOBUF_SSTL3_I
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL3_I : component is true;
component IOBUF_SSTL3_II
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL3_II : component is true;
component IOBUF_SSTL3_II_DCI
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_SSTL3_II_DCI : component is true;
component IOBUF_S_12
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_12 : component is true;
component IOBUF_S_16
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_16 : component is true;
component IOBUF_S_2
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_2 : component is true;
component IOBUF_S_24
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_24 : component is true;
component IOBUF_S_4
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_4 : component is true;
component IOBUF_S_6
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_6 : component is true;
component IOBUF_S_8
 port (
   O : out std_logic;
   IO : inout std_logic;
   I : in std_logic;
   T : in std_logic
 );
end component;
attribute syn_black_box of IOBUF_S_8 : component is true;
component KEEPER
 port (
   O : inout std_logic
 );
end component;
attribute syn_black_box of KEEPER : component is true;
attribute syn_noprune of KEEPER : component is true;
component LD
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic
 );
end component;
attribute syn_black_box of LD : component is true;
component LDC
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic
 );
end component;
attribute syn_black_box of LDC : component is true;
component LDCE
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic
 );
end component;
attribute syn_black_box of LDCE : component is true;
component LDCE_1
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic
 );
end component;
attribute syn_black_box of LDCE_1 : component is true;
component LDCP
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDCP : component is true;
component LDCPE
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDCPE : component is true;
component LDCPE_1
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDCPE_1 : component is true;
component LDCP_1
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDCP_1 : component is true;
component LDC_1
 port (
   Q : out std_logic;
   CLR : in std_logic;
   D : in std_logic;
   G : in std_logic
 );
end component;
attribute syn_black_box of LDC_1 : component is true;
component LDE
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic
 );
end component;
attribute syn_black_box of LDE : component is true;
component LDE_1
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic
 );
end component;
attribute syn_black_box of LDE_1 : component is true;
component LDP
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDP : component is true;
component LDPE
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDPE : component is true;
component LDPE_1
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   GE : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDPE_1 : component is true;
component LDP_1
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic;
   PRE : in std_logic
 );
end component;
attribute syn_black_box of LDP_1 : component is true;
component LD_1
 port (
   Q : out std_logic;
   D : in std_logic;
   G : in std_logic
 );
end component;
attribute syn_black_box of LD_1 : component is true;
component LUT1
 generic(INIT : bit_vector := "00");
 port (
   O : out std_logic;
   I0 : in std_logic
 );
end component;
attribute syn_black_box of LUT1 : component is true;
attribute xc_map of LUT1 : component is "lut";
component LUT1_D
 generic(INIT : bit_vector := "00");
 port (
   LO : out std_logic;
   O : out std_logic;
   I0 : in std_logic
 );
end component;
attribute syn_black_box of LUT1_D : component is true;
attribute xc_map of LUT1_D : component is "lut";
component LUT1_L
 generic(INIT : bit_vector := "00");
 port (
   LO : out std_logic;
   I0 : in std_logic
 );
end component;
attribute syn_black_box of LUT1_L : component is true;
attribute xc_map of LUT1_L : component is "lut";
component LUT2
 generic(INIT : bit_vector := X"0");
 port (
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of LUT2 : component is true;
attribute xc_map of LUT2 : component is "lut";
component LUT2_D
 generic(INIT : bit_vector := X"0");
 port (
   LO : out std_logic;
   O : out std_logic;
   I0 : in std_logic;
   I1 : in std_logic
 );
end component;
attribute syn_black_box of LUT2_D : component is true;
attribute xc_map of LUT2_D : component is "lut";
component L