infrastructure_iobs_48bit.vhd

XILINX memory interface generator. XILINX的外部存储器接口。

                        CE => vcc,
                        D0 => gnd,
                        D1 => vcc,
                         R => gnd,
                         S => gnd);

U11 : FDDRRSE port map (
                        Q => ddr2_clk5_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => vcc,
                        D1 => gnd,
                         R => gnd,
                         S => gnd);

U12 : FDDRRSE port map (
                        Q => ddr2_clk5b_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => gnd,
                        D1 => vcc,
                         R => gnd,
                         S => gnd);

U13 : FDDRRSE port map (
                        Q => ddr2_clk6_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => vcc,
                        D1 => gnd,
                         R => gnd,
                         S => gnd);

U14 : FDDRRSE port map (
                        Q => ddr2_clk6b_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => gnd,
                        D1 => vcc,
                         R => gnd,
                         S => gnd);

U15 : FDDRRSE port map (
                        Q => ddr2_clk7_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => vcc,
                        D1 => gnd,
                         R => gnd,
                         S => gnd);

U16 : FDDRRSE port map (
                        Q => ddr2_clk7b_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => gnd,
                        D1 => vcc,
                         R => gnd,
                         S => gnd);

U17 : FDDRRSE port map (
                        Q => ddr2_clk8_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => vcc,
                        D1 => gnd,
                         R => gnd,
                         S => gnd);

U18 : FDDRRSE port map (
                        Q => ddr2_clk8b_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => gnd,
                        D1 => vcc,
                         R => gnd,
                         S => gnd);

U19 : FDDRRSE port map (
                        Q => ddr2_clk9_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => vcc,
                        D1 => gnd,
                         R => gnd,
                         S => gnd);

U20 : FDDRRSE port map (
                        Q => ddr2_clk9b_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => gnd,
                        D1 => vcc,
                         R => gnd,
                         S => gnd);

U21 : FDDRRSE port map (
                        Q => ddr2_clk10_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => vcc,
                        D1 => gnd,
                         R => gnd,
                         S => gnd);

U22 : FDDRRSE port map (
                        Q => ddr2_clk10b_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => gnd,
                        D1 => vcc,
                         R => gnd,
                         S => gnd);

U23 : FDDRRSE port map (
                        Q => ddr2_clk11_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => vcc,
                        D1 => gnd,
                         R => gnd,
                         S => gnd);

U24 : FDDRRSE port map (
                        Q => ddr2_clk11b_q ,
                        C0 => clk0,
                        C1 => clk180,
                        CE => vcc,
                        D0 => gnd,
                        D1 => vcc,
                         R => gnd,
                         S => gnd);

---- ******************************************
---- Ouput BUffers for ddr clk's 
---- ******************************************


r1 : OBUF port map (
                     I => ddr2_clk0_q,
                     O => ddr2_clk0);

r2 : OBUF port map (
                     I => ddr2_clk0b_q,
                     O => ddr2_clk0b);

r3 : OBUF port map (
                     I => ddr2_clk1_q,
                     O => ddr2_clk1);

r4 : OBUF port map (
                     I => ddr2_clk1b_q,
                     O => ddr2_clk1b);

r5 : OBUF port map (
                     I => ddr2_clk2_q,
                     O => ddr2_clk2);

r6 : OBUF port map (
                     I => ddr2_clk2b_q,
                     O => ddr2_clk2b);

r7 : OBUF port map (
                     I => ddr2_clk3_q,
                     O => ddr2_clk3);

r8 : OBUF port map (
                     I => ddr2_clk3b_q,
                     O => ddr2_clk3b);

r9 : OBUF port map (
                     I => ddr2_clk4_q,
                     O => ddr2_clk4);

r10 : OBUF port map (
                     I => ddr2_clk4b_q,
                     O => ddr2_clk4b);


r11 : OBUF port map (
                     I => ddr2_clk5_q,
                     O => ddr2_clk5);

r12 : OBUF port map (
                     I => ddr2_clk5b_q,
                     O => ddr2_clk5b);

r13 : OBUF port map (
                     I => ddr2_clk6_q,
                     O => ddr2_clk6);

r14 : OBUF port map (
                     I => ddr2_clk6b_q,
                     O => ddr2_clk6b);

r15 : OBUF port map (
                     I => ddr2_clk7_q,
                     O => ddr2_clk7);

r16 : OBUF port map (
                     I => ddr2_clk7b_q,
                     O => ddr2_clk7b);

r17 : OBUF port map (
                     I => ddr2_clk8_q,
                     O => ddr2_clk8);

r18 : OBUF port map (
                     I => ddr2_clk8b_q,
                     O => ddr2_clk8b);
r19 : OBUF port map (
                     I => ddr2_clk9_q,
                     O => ddr2_clk9);

r20 : OBUF port map (
                     I => ddr2_clk9b_q,
                     O => ddr2_clk9b);

r21 : OBUF port map (
                     I => ddr2_clk10_q,
                     O => ddr2_clk10);

r22 : OBUF port map (
                     I => ddr2_clk10b_q,
                     O => ddr2_clk10b);

r23 : OBUF port map (
                     I => ddr2_clk11_q,
                     O => ddr2_clk11);

r24 : OBUF port map (
                     I => ddr2_clk11b_q,
                     O => ddr2_clk11b);


end   arc_infrastructure_iobs_48bit;