data_read_controller_40bit.v

来自「XILINX memory interface generator. XILI」· Verilog 代码 · 共 46 行

//--******************************************************************************
//--
//--  Xilinx, Inc. 2002                 www.xilinx.com
//--
//-- 
//--*******************************************************************************
//--
//--    File   name   :   data_read_controller_40bit.v.v 
//--
//--  Description :     This module generates all the control signals  for the 
//--                     read data path.
//-- 
//--                    
//--  Date - revision : 10/16/2003
//--
//--  Author :          Maria George ( Modified by Sailaja)
//--
//--  Contact : e-mail  [e-mail]
//--            phone   + 1 800 255 7778 
//--
//--  Disclaimer: LIMITED WARRANTY AND DISCLAMER. These designs are 
//--              provided to you "as is". Xilinx and its licensors make and you 
//--              receive no warranties or conditions, express, implied, 
//--              statutory or otherwise, and Xilinx specifically disclaims any 
//--              implied warranties of merchantability, non-infringement, or 
//--              fitness for a particular purpose. Xilinx does not warrant that 
//--              the functions contained in these designs will meet your 
//--              requirements, or that the operation of these designs will be 
//--              uninterrupted or error free, or that defects in the Designs 
//--              will be corrected. Furthermore, Xilinx does not warrant or 
//--              make any representations regarding use or the results of the 
//--              use of the designs in terms of correctness, accuracy, 
//--              reliability, or otherwise. 
//--
//--              LIMITATION OF LIABILITY. In no event will Xilinx or its 
//--              licensors be liable for any loss of data, lost profits, cost 
//--              or procurement of substitute goods or services, or for any 
//--              special, incidental, consequential, or indirect damages 
//--              arising from the use or operation of the designs or 
//--              accompanying documentation, however caused and on any theory 
//--              of liability. This limitation will apply even if Xilinx 
//--              has been advised of the possibility of such damage. This 
//--              limitation shall apply not-withstanding the failure of the 
//--              essential purpose of any limited remedies herein. 
//--
//--  Copyright