data_write_40bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

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//  Xilinx, Inc. 2002                 www.xilinx.com
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//
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//    File   name   :   data_write_40bit.v.v 
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//  Description :     This module comprises the write data paths for the
//                    DDR1 memory interface.                 
// 
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//  Date - revision : 10/16/2003
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//  Author :          Maria George (Modifed by Sailaja)
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//  Contact : e-mail  [e-mail]
//            phone   + 1 800 255 7778 
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