infrastructure_iobs.v

XILINX memory interface generator. XILINX的外部存储器接口。

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//  Xilinx, Inc. 2002                 www.xilinx.com
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//  File name :       infrastructure_iobs.v
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//  Description :     This module instantiates DDR IOB output flip-flops, an 
//                    output buffer with registered tri-state, and an input buffer  
//                    for a single strobe/dqs bit. The DDR IOB output flip-flops 
//                    are used to forward strobe to memory during a write. During
//                    a read, the output of the IBUF is routed to the internal 
//                    delay module, dqs_delay. 
//                    
//  Date - revision : 12/10/2003
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//  Author :          Maria George
//
//  Contact : e-mail  [e-mail]
//            phone   + 1 800 255 7778 
//
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