ddr2_top_32bit.v

XILINX memory interface generator. XILINX的外部存储器接口。

//******************************************************************************
//
//  Xilinx, Inc. 2002                 www.xilinx.com
//
//  XAPP 253 - Synthesizable DDR SDRAM Controller
//
//*******************************************************************************
//
//  File name :       ddr2_top
//
//  Description :     
//                    Main DDR SDRAM controller block. This includes the following
//                    features:
//                    - The main controller state machine that controlls the 
//                    initialization process upon power up, as well as the 
//                    read, write, and refresh commands. 
//                    - handles the data path during READ and WRITEs.
//                    - Generates control signals for other modules, including the
//                      data strobe(DQS) signal
//
//  Date - revision : 05/01/2002
//
//  Author :          Modified by Sailaja
//
//  Contact : e-mail  [e-mail]
//            phone   + 1 800 255 7778 
//
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//              fitness for a particular purpose. Xilinx does not warrant that 
//              the functions contained in these designs will meet your 
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//
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