ep1c6_32_vga.hier_info

VHDL入门实验。256色VGA显示驱动 开发软件Quartus II 6.0 芯片EP2c8Q208

|vga
clock => pll:U1.inclk0
disp_dato[0] <= disp_dato~7.DB_MAX_OUTPUT_PORT_TYPE
disp_dato[1] <= disp_dato~6.DB_MAX_OUTPUT_PORT_TYPE
disp_dato[2] <= disp_dato~5.DB_MAX_OUTPUT_PORT_TYPE
disp_dato[3] <= disp_dato~4.DB_MAX_OUTPUT_PORT_TYPE
disp_dato[4] <= disp_dato~3.DB_MAX_OUTPUT_PORT_TYPE
disp_dato[5] <= disp_dato~2.DB_MAX_OUTPUT_PORT_TYPE
disp_dato[6] <= disp_dato~1.DB_MAX_OUTPUT_PORT_TYPE
disp_dato[7] <= disp_dato~0.DB_MAX_OUTPUT_PORT_TYPE
hsync <= LessThan4.DB_MAX_OUTPUT_PORT_TYPE
vsync <= LessThan5.DB_MAX_OUTPUT_PORT_TYPE


|vga|pll:U1
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]


|vga|pll:U1|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => ~NO_FANOUT~
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= <UNC>
clk[2] <= <UNC>
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE