ep1c6_32_vga.map.qmsg

VHDL入门实验。256色VGA显示驱动 开发软件Quartus II 6.0 芯片EP2c8Q208

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Dec 28 20:28:13 2008 " "Info: Processing started: Sun Dec 28 20:28:13 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ep1c6_32_vga -c ep1c6_32_vga " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ep1c6_32_vga -c ep1c6_32_vga" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "vga.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file vga.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 vga-one " "Info: Found design unit 1: vga-one" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 35 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 vga " "Info: Found entity 1: vga" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 26 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "vga " "Info: Elaborating entity \"vga\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "pll.vhd 2 1 " "Warning: Using design file pll.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pll-SYN " "Info: Found design unit 1: pll-SYN" {  } { { "pll.vhd" "" { Text "E:/ep1c6_32_vga/pll.vhd" 48 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 pll " "Info: Found entity 1: pll" {  } { { "pll.vhd" "" { Text "E:/ep1c6_32_vga/pll.vhd" 39 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pll pll:U1 " "Info: Elaborating entity \"pll\" for hierarchy \"pll:U1\"" {  } { { "vga.vhd" "U1" { Text "E:/ep1c6_32_vga/vga.vhd" 70 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus60/libraries/megafunctions/altpll.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus60/libraries/megafunctions/altpll.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll " "Info: Found entity 1: altpll" {  } { { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 365 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll pll:U1\|altpll:altpll_component " "Info: Elaborating entity \"altpll\" for hierarchy \"pll:U1\|altpll:altpll_component\"" {  } { { "pll.vhd" "altpll_component" { Text "E:/ep1c6_32_vga/pll.vhd" 129 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_ELABORATION_HEADER" "pll:U1\|altpll:altpll_component " "Info: Elaborated megafunction instantiation \"pll:U1\|altpll:altpll_component\"" {  } { { "pll.vhd" "" { Text "E:/ep1c6_32_vga/pll.vhd" 129 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "h_dat\[0\] h_dat\[1\] " "Info: Duplicate register \"h_dat\[0\]\" merged to single register \"h_dat\[1\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 149 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "h_dat\[3\] h_dat\[2\] " "Info: Duplicate register \"h_dat\[3\]\" merged to single register \"h_dat\[2\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 149 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "h_dat\[4\] h_dat\[2\] " "Info: Duplicate register \"h_dat\[4\]\" merged to single register \"h_dat\[2\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 149 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "h_dat\[6\] h_dat\[5\] " "Info: Duplicate register \"h_dat\[6\]\" merged to single register \"h_dat\[5\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 149 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "h_dat\[7\] h_dat\[5\] " "Info: Duplicate register \"h_dat\[7\]\" merged to single register \"h_dat\[5\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 149 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "v_dat\[1\] v_dat\[0\] " "Info: Duplicate register \"v_dat\[1\]\" merged to single register \"v_dat\[0\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 126 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "v_dat\[3\] v_dat\[2\] " "Info: Duplicate register \"v_dat\[3\]\" merged to single register \"v_dat\[2\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 126 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "v_dat\[4\] v_dat\[2\] " "Info: Duplicate register \"v_dat\[4\]\" merged to single register \"v_dat\[2\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 126 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "v_dat\[6\] v_dat\[5\] " "Info: Duplicate register \"v_dat\[6\]\" merged to single register \"v_dat\[5\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 126 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "v_dat\[7\] v_dat\[5\] " "Info: Duplicate register \"v_dat\[7\]\" merged to single register \"v_dat\[5\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 126 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[1\] data\[0\] " "Info: Duplicate register \"data\[1\]\" merged to single register \"data\[0\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 114 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[3\] data\[2\] " "Info: Duplicate register \"data\[3\]\" merged to single register \"data\[2\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 114 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[4\] data\[2\] " "Info: Duplicate register \"data\[4\]\" merged to single register \"data\[2\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 114 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[6\] data\[5\] " "Info: Duplicate register \"data\[6\]\" merged to single register \"data\[5\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 114 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0} { "Info" "IOPT_MLS_DUP_REG_INFO" "data\[7\] data\[5\] " "Info: Duplicate register \"data\[7\]\" merged to single register \"data\[5\]\"" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 114 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "106 " "Info: Implemented 106 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "1 " "Info: Implemented 1 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "94 " "Info: Implemented 94 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0} { "Info" "ISCL_SCL_TM_PLLS" "1 " "Info: Implemented 1 ClockLock PLLs" {  } {  } 0 0 "Implemented %1!d! ClockLock PLLs" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 1  Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Dec 28 20:28:17 2008 " "Info: Processing ended: Sun Dec 28 20:28:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}