ep1c6_32_vga.tan.qmsg

VHDL入门实验。256色VGA显示驱动 开发软件Quartus II 6.0 芯片EP2c8Q208

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pll:U1\|altpll:altpll_component\|_clk0 register vcount\[5\] register timer\[1\] 33.493 ns " "Info: Slack time is 33.493 ns for clock \"pll:U1\|altpll:altpll_component\|_clk0\" between source register \"vcount\[5\]\" and destination register \"timer\[1\]\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "153.68 MHz 6.507 ns " "Info: Fmax is 153.68 MHz (period= 6.507 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "39.738 ns + Largest register register " "Info: + Largest register to register requirement is 39.738 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "40.000 ns + " "Info: + Setup relationship between source and destination is 40.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 40.000 ns " "Info: + Latch edge is 40.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll:U1\|altpll:altpll_component\|_clk0 40.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"pll:U1\|altpll:altpll_component\|_clk0\" is 40.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Destination 0.000 ns 0.000 degrees " "Info: Clock offset from Destination is based on specified offset of 0.000 ns and phase shift of 0.000 degrees of the derived clock" {  } {  } 0 0 "Clock offset from %1!s! is based on specified offset of %2!s! and phase shift of %3!s! of the derived clock" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll:U1\|altpll:altpll_component\|_clk0 40.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"pll:U1\|altpll:altpll_component\|_clk0\" is 40.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_CLOCK_OFFSET_COMPONENTS" "Source 0.000 ns 0.000 degrees " "Info: Clock offset from Source is based on specified offset of 0.000 ns and phase shift of 0.000 degrees of the derived clock" {  } {  } 0 0 "Clock offset from %1!s! is based on specified offset of %2!s! and phase shift of %3!s! of the derived clock" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.002 ns + Largest " "Info: + Largest clock skew is 0.002 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:U1\|altpll:altpll_component\|_clk0 destination 2.501 ns + Shortest register " "Info: + Shortest clock path from clock \"pll:U1\|altpll:altpll_component\|_clk0\" to destination register is 2.501 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:U1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:U1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll:U1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns pll:U1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 40 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 40; COMB Node = 'pll:U1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.916 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.919 ns) + CELL(0.666 ns) 2.501 ns timer\[1\] 3 REG LCFF_X25_Y16_N13 2 " "Info: 3: + IC(0.919 ns) + CELL(0.666 ns) = 2.501 ns; Loc. = LCFF_X25_Y16_N13; Fanout = 2; REG Node = 'timer\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.585 ns" { pll:U1|altpll:altpll_component|_clk0~clkctrl timer[1] } "NODE_NAME" } } { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 26.63 % ) " "Info: Total cell delay = 0.666 ns ( 26.63 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.835 ns ( 73.37 % ) " "Info: Total interconnect delay = 1.835 ns ( 73.37 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.501 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl timer[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.501 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl timer[1] } { 0.000ns 0.916ns 0.919ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll:U1\|altpll:altpll_component\|_clk0 source 2.499 ns - Longest register " "Info: - Longest clock path from clock \"pll:U1\|altpll:altpll_component\|_clk0\" to source register is 2.499 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll:U1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll:U1\|altpll:altpll_component\|_clk0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll:U1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.916 ns) + CELL(0.000 ns) 0.916 ns pll:U1\|altpll:altpll_component\|_clk0~clkctrl 2 COMB CLKCTRL_G3 40 " "Info: 2: + IC(0.916 ns) + CELL(0.000 ns) = 0.916 ns; Loc. = CLKCTRL_G3; Fanout = 40; COMB Node = 'pll:U1\|altpll:altpll_component\|_clk0~clkctrl'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.916 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl } "NODE_NAME" } } { "altpll.tdf" "" { Text "d:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.917 ns) + CELL(0.666 ns) 2.499 ns vcount\[5\] 3 REG LCFF_X26_Y15_N21 9 " "Info: 3: + IC(0.917 ns) + CELL(0.666 ns) = 2.499 ns; Loc. = LCFF_X26_Y15_N21; Fanout = 9; REG Node = 'vcount\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.583 ns" { pll:U1|altpll:altpll_component|_clk0~clkctrl vcount[5] } "NODE_NAME" } } { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.666 ns ( 26.65 % ) " "Info: Total cell delay = 0.666 ns ( 26.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.833 ns ( 73.35 % ) " "Info: Total interconnect delay = 1.833 ns ( 73.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.499 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl vcount[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.499 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl vcount[5] } { 0.000ns 0.916ns 0.917ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.501 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl timer[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.501 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl timer[1] } { 0.000ns 0.916ns 0.919ns } { 0.000ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.499 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl vcount[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.499 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl vcount[5] } { 0.000ns 0.916ns 0.917ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.304 ns - " "Info: - Micro clock to output delay of source is 0.304 ns" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 84 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.040 ns - " "Info: - Micro setup delay of destination is -0.040 ns" {  } { { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 104 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.501 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl timer[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.501 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl timer[1] } { 0.000ns 0.916ns 0.919ns } { 0.000ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.499 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl vcount[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.499 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl vcount[5] } { 0.000ns 0.916ns 0.917ns } { 0.000ns 0.000ns 0.666ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.245 ns - Longest register register " "Info: - Longest register to register delay is 6.245 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vcount\[5\] 1 REG LCFF_X26_Y15_N21 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y15_N21; Fanout = 9; REG Node = 'vcount\[5\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { vcount[5] } "NODE_NAME" } } { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 84 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.498 ns) + CELL(0.370 ns) 1.868 ns h_dat~1448 2 COMB LCCOMB_X25_Y16_N30 1 " "Info: 2: + IC(1.498 ns) + CELL(0.370 ns) = 1.868 ns; Loc. = LCCOMB_X25_Y16_N30; Fanout = 1; COMB Node = 'h_dat~1448'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.868 ns" { vcount[5] h_dat~1448 } "NODE_NAME" } } { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 48 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.836 ns) + CELL(0.206 ns) 3.910 ns Equal1~59 3 COMB LCCOMB_X25_Y16_N6 3 " "Info: 3: + IC(1.836 ns) + CELL(0.206 ns) = 3.910 ns; Loc. = LCCOMB_X25_Y16_N6; Fanout = 3; COMB Node = 'Equal1~59'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.042 ns" { h_dat~1448 Equal1~59 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.371 ns) + CELL(0.206 ns) 4.487 ns Equal1~61 4 COMB LCCOMB_X25_Y16_N2 7 " "Info: 4: + IC(0.371 ns) + CELL(0.206 ns) = 4.487 ns; Loc. = LCCOMB_X25_Y16_N2; Fanout = 7; COMB Node = 'Equal1~61'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.577 ns" { Equal1~59 Equal1~61 } "NODE_NAME" } } { "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/quartus60/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.374 ns) + CELL(0.206 ns) 5.067 ns process2~0 5 COMB LCCOMB_X25_Y16_N0 9 " "Info: 5: + IC(0.374 ns) + CELL(0.206 ns) = 5.067 ns; Loc. = LCCOMB_X25_Y16_N0; Fanout = 9; COMB Node = 'process2~0'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.580 ns" { Equal1~61 process2~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.323 ns) + CELL(0.855 ns) 6.245 ns timer\[1\] 6 REG LCFF_X25_Y16_N13 2 " "Info: 6: + IC(0.323 ns) + CELL(0.855 ns) = 6.245 ns; Loc. = LCFF_X25_Y16_N13; Fanout = 2; REG Node = 'timer\[1\]'" {  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.178 ns" { process2~0 timer[1] } "NODE_NAME" } } { "vga.vhd" "" { Text "E:/ep1c6_32_vga/vga.vhd" 104 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.843 ns ( 29.51 % ) " "Info: Total cell delay = 1.843 ns ( 29.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.402 ns ( 70.49 % ) " "Info: Total interconnect delay = 4.402 ns ( 70.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.245 ns" { vcount[5] h_dat~1448 Equal1~59 Equal1~61 process2~0 timer[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.245 ns" { vcount[5] h_dat~1448 Equal1~59 Equal1~61 process2~0 timer[1] } { 0.000ns 1.498ns 1.836ns 0.371ns 0.374ns 0.323ns } { 0.000ns 0.370ns 0.206ns 0.206ns 0.206ns 0.855ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.501 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl timer[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.501 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl timer[1] } { 0.000ns 0.916ns 0.919ns } { 0.000ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.499 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl vcount[5] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "2.499 ns" { pll:U1|altpll:altpll_component|_clk0 pll:U1|altpll:altpll_component|_clk0~clkctrl vcount[5] } { 0.000ns 0.916ns 0.917ns } { 0.000ns 0.000ns 0.666ns } } } { "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.245 ns" { vcount[5] h_dat~1448 Equal1~59 Equal1~61 process2~0 timer[1] } "NODE_NAME" } } { "d:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus60/win/Technology_Viewer.qrui" "6.245 ns" { vcount[5] h_dat~1448 Equal1~59 Equal1~61 process2~0 timer[1] } { 0.000ns 1.498ns 1.836ns 0.371ns 0.374ns 0.323ns } { 0.000ns 0.370ns 0.206ns 0.206ns 0.206ns 0.855ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clock " "Info: No valid register-to-register data paths exist for clock \"clock\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}