gate_and2.vhd

来自「采用VHDL语言编写的万年历程序」· VHDL 代码 · 共 17 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity gate_and2 is
    Port ( in1 : in std_logic;
           in2 : in std_logic;
           out1 : out std_logic);
end gate_and2;

architecture Behavioral of gate_and2 is

begin
   out1<=in1 and in2;
end Behavioral;