counter.vhd

来自「采用VHDL语言编写的万年历程序」· VHDL 代码 · 共 57 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter is
    Port ( reset:in std_logic;
           clk : in std_logic;
           outh : out std_logic_vector(3 downto 0);
           outmh : out std_logic_vector(3 downto 0);
           outml:out std_logic_vector(3 downto 0);
			  outl:out std_logic_vector(3 downto 0));
end counter;

architecture Behavioral of counter is

begin
    process(clk,reset)
	 variable countl,counth,countmh,countml:std_logic_vector(3 downto 0);
	 begin
	    if reset='0'then
		    counth:="0000";
			 countmh:="0000";
          countml:="0000";
			 countl:="0000";
			 outh<="0000";
			 outmh<="0000";
			 outml<="0000";
			 outl<="0000";
		 elsif clk'event and clk='1'then
			 if countl="1001"then
			    countl:="0000";
				 countml:=countml+1;
			 else 
			    countl:=countl+1;
			 end if;
          if countml="1010"then
			    countml:="0000";
				 countmh:=countmh+1;
			 end if;
			 if countmh="1010"then
			    countmh:="0000";
				 counth:=counth+1;
			 end if;
			 if counth="1010"then
			    counth:="0000";
			 end if;
		 end if;
		 outl<=countl;
		 outh<=counth;
		 outml<=countml;
		 outmh<=countmh;
	 end process;


end Behavioral;