triangle.vhd

来自「采用VHDL语言写了一个函数发生器的程序。内含有各个模块」· VHDL 代码 · 共 39 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity triangle is
    Port (clock,reset :in std_logic;
	       dd:out std_logic_vector(8 downto 0));
end triangle;

architecture Behavioral of triangle is
SIGNAL   Qt : INTEGER RANGE 200 DOWNTO -1 ;
 
 signal clk:std_logic;
 type state is (st1,st2);
 signal current :state;
begin

PROCESS(clock,Qt)
    BEGIN
	 if reset='0' then
	   Qt<=0;
		current<=st1;
	 elsif rising_edge(clock) then
	  case current is
  	  when st1 => Qt<=Qt+1;
	              if Qt>180 then current<=st2;
					  end if;
	  when st2 =>Qt<=Qt-1;
	              if Qt<1 then current <=st1;
					  end if;
	  end case;
		  end if;
		 

    END PROCESS;
 dd<=conv_std_logic_vector(Qt,9);
end Behavioral;