div_m.vhd

来自「采用VHDL语言写了一个函数发生器的程序。内含有各个模块」· VHDL 代码 · 共 36 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity div_m is
    Port (clk_in,reset : in std_logic;
	       clk_out : out std_logic);
end div_m;

architecture Behavioral of div_m is

begin
process(clk_in,reset)
 variable count2: integer;
		variable clk0: std_logic;
		begin
		   if  reset='0' then
			 count2:=0;
			 clk0:='0';
			 elsif clk_in'event and clk_in='1' then
			  count2:=count2+1;
			  if count2=1600 then
			  clk0:='1';
			  elsif count2=3200then
			    count2:=0;
				 clk0:='0';
		     --end if;
			 end if;
			end if;
		clk_out<=clk0;

end process;

end Behavioral;