function_generator.npl

采用VHDL语言写了一个函数发生器的程序。内含有各个模块

JDF E
// Created by ISE ver 1.0
PROJECT function_generator
DESIGN function_generator Normal
DEVKIT xc2s100-5pq208
DEVFAM spartan2
FLOW XST VHDL
STIMULUS ff.tbw Normal
STIMULUS ll.tbw Normal
MODULE count1.vhd
MODSTYLE count1 Normal
MODULE choice_function.vhd
MODSTYLE choice_function Normal
MODULE dactext.vhd
MODSTYLE dactext Normal
MODULE div360.vhd
MODSTYLE div360 Normal
MODULE div180.vhd
MODSTYLE div180 Normal
MODULE choice.vhd
MODSTYLE choice Normal
MODULE rectangular.vhd
MODSTYLE rectangular Normal
MODULE aslant.vhd
MODSTYLE aslant Normal
MODULE show.vhd
MODSTYLE show Normal
MODULE div.vhd
MODSTYLE div Normal
MODULE triangle.vhd
MODSTYLE triangle Normal
MODULE top.vhd
MODSTYLE top Normal
MODULE key.vhd
MODSTYLE key Normal

[Normal]
xilxBitgStart_Clk=xstvhd, SPARTAN2, Implementation.t_bitFile, 1059035526, JTAG Clock

[STRATEGY-LIST]
Normal=True, 1059011874