key.vhd

来自「采用VHDL语言写了一个函数发生器的程序。内含有各个模块」· VHDL 代码 · 共 48 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity key is
    Port (clk3200,key,reset: in std_logic;
	       led1,led2,led3,led4:out std_logic);
end key;

architecture Behavioral of key is
type state is (st1,st2);
signal current :state;
signal clkout:std_logic;
begin


process(key,clk3200)
variable cnt :integer range 4 downto 0 ;
begin
if reset='0' then
cnt:=0;
current<=st1;
led1<='1';led2<='1';led3<='1';led4<='1';
elsif rising_edge(clk3200) then

 case current is
   when st1 =>if key='0' then current<=st2;
	            end if;  
   when st2 =>if key='1' then 
	           cnt:=cnt+1;
				  case cnt is
				  when 1=>led1<='0';led2<='1';led3<='1';led4<='1';current<=st1;
              when 2=>led1<='1';led2<='0';led3<='1';led4<='1';current<=st1;
              when 3=>led1<='1';led2<='1';led3<='0';led4<='1';current<=st1;
				  when 4=>led1<='1';led2<='1';led3<='1';led4<='0';cnt:=0;current<=st1;
				  when others =>null;
				   
				  end case;
				end if;
   when others=>null;
 end case;
 end if;

end process;
end Behavioral;