top.vhd

采用VHDL语言写了一个函数发生器的程序。内含有各个模块

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity top is
    Port (sysclk,reset,add,sub,step,key_function:in std_logic;
	       w1,w2,w3,w4,led_th,led_hu,led_ten,led_one:out std_logic;
			 step1,step10,step100,step1000:buffer std_logic;
			 led_data :out std_logic_vector( 6 downto 0);
			 DD : out std_logic_vector(8 downto 0));
end top;

architecture Behavioral of top is


component div 
 Port (sysclk,reset,add,sub,step1,step10,step100,step1000 :in std_logic;
         
		
			 clkout:out std_logic;
			 clk3200,clk100:out std_logic);
end component;

component key
  Port (clk3200,key,reset: in std_logic;
	       led1,led2,led3,led4:out std_logic);
end component;

component show
Port (   clk3200 :in std_logic;
	        reset :in std_logic;
	          show_th,show_hu,show_ten,show_one: in std_logic_vector(3 downto 0);
	          led_data:out std_logic_vector(6 downto 0);
	          w1,w2,w3,w4:out std_logic);
end component;
component dactext
 PORT ( clock: IN STD_LOGIC;
        
       DD : out std_logic_vector(8 downto 0)
		);
end component;
component count1
  Port (sysclk,clk,reset :in std_logic;
         
      led_th,led_hu,led_ten,led_one :out std_logic;
		showone,showten,showhu,showth :out std_logic_vector(3 downto 0)

      );
end component;
component aslant
Port (clock,reset :in std_logic;
	       dd:out std_logic_vector(8 downto 0));

end component;
component choice
Port (key_route,reset,clk3200,clk_sin,clk_tri,clk_asl,clk_rectangular: in std_logic;
	       clk :out std_logic);

end component;
component choice_function
Port (clk3200,reset,key_route:in std_logic;
	       sin_data,tri_data,asl_data,rec_data:in std_logic_vector(8 downto 0);
			 function_data: out std_logic_vector(8 downto 0));

end component;
component rectangular
Port (clkout,reset :in std_logic;
	       dd:out std_logic_vector(8 downto 0)); 

end component;
component div360
  Port (clk_in,reset : in std_logic;
	       clk_out : out std_logic);

end component;
component div180
Port (clk_in,reset : in std_logic;
	       clk_out : out std_logic);

end component;
component triangle
Port (clock,reset :in std_logic;
	       dd:out std_logic_vector(8 downto 0));
end component;
signal sysclk_p,reset_p,clk_test,test1,clk3200_p,clkout_p,clk_p,step1_p,step10_p,step100_p,step1000_p,clk100_p :std_logic;

signal clk_sin_pp,clk_tri_pp,clk_asl_pp,clk_rectangular_pp :std_logic;
signal show_th_p,show_hu_p,show_ten_p,show_one_p:std_logic_vector(3 downto 0);
signal sin_p,rec_p,tri_p,asl_p,test:std_logic_vector(8 downto 0);
begin

div_u :div port map (sysclk=>sysclk,reset=>reset,add=>add,sub=>sub,
                      step1=>step1_p,step10=>step10_p,step100=>step100_p,step1000=>step1000_p,
							 clkout=>clkout_p,clk3200=>clk3200_p,clk100=>clk100_p);
key_u : key port map (clk3200=>clk3200_p,reset=>reset,key=>step,led1=>step1000_p,led2=>step100_p,
                         led3=>step10_p,led4=>step1_p);
show_u :show port map (clk3200=>clk3200_p,reset=>reset,show_th=>show_th_p,show_hu=>show_hu_p,
                        show_ten=>show_ten_p,show_one=>show_one_p,led_data=>led_data,
								w1=>w1,w2=>w2,w3=>w3,w4=>w4);
dactext_u : dactext port map (clock=>clkout_p,DD=>sin_p);
count1_u : count1 port map (sysclk=>sysclk,clk=>clk_test,reset=>reset,led_th=>led_th,
                            led_hu=>led_hu,led_ten=>led_ten,led_one=>led_one,
									 showone=>show_one_p,showten=>show_ten_p,showhu=>show_hu_p,showth=>show_th_p);
aslant_u : aslant port map (clock=>clkout_p,reset=>reset,dd=>asl_p);
choice_u : choice port map (key_route=>key_function,clk3200=>clk100_p,reset=>reset,clk_sin=>clk_sin_pp,
                            clk_tri=>clk_sin_pp,clk_asl=>clk_asl_pp,clk_rectangular=>clk_rectangular_pp,clk=>clk_test);
choice_function_u :choice_function port map(clk3200=>clk100_p,reset=>reset,key_route=>key_function,
                           sin_data=>sin_p,tri_data=>tri_p,asl_data=>asl_p,rec_data=>rec_p,function_data=>DD);
div360_u1  :div360 port map (clk_in=>clkout_p,reset=>reset,clk_out=>clk_sin_pp);

div360_u3 : div360 port map (clk_in=>clkout_p,reset=>reset,clk_out=>clk_rectangular_pp);
div180_u : div180 port map (clk_in=>clkout_p,reset=>reset,clk_out=>clk_asl_pp);

rectangular_u : rectangular port map (clkout=>clkout_p,dd=>rec_p,reset=>reset);

triangle_u :triangle port map (clock=>clkout_p,reset=>reset,DD=>tri_p);


step1<=step1_p;
step10<=step10_p;
step100<=step100_p;
step1000<=step1000_p;

end Behavioral;