📄 count1.vhd
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity count1 is
Port (sysclk,clk,reset :in std_logic;
led_th,led_hu,led_ten,led_one :out std_logic;
showone,showten,showhu,showth :out std_logic_vector(3 downto 0)
);
end count1;
architecture Behavioral of count1 is
signal clkk :std_logic;
signal million,hu_th1,ten_th1,th1,hu1,ten1,one1 : std_logic_vector(3 downto 0);
begin
process(sysclk,reset)
variable count2: integer;
variable clk0: std_logic;
begin
if reset='0' then
count2:=0;
clk0:='0';
elsif sysclk'event and sysclk='1' then
count2:=count2+1;
if count2=32000000 then
clk0:='1';
elsif count2=64000000 then
count2:=0;
clk0:='0';
--end if;
end if;
end if;
clkk<=clk0;
end process ;
counter9999:process(clk,clkk)
begin
if( clkk='0') then
million<="0000";
hu_th1<="0000";
ten_th1<="0000";
th1<="0000";
hu1<="0000";
ten1<="0000";
one1<="0000";
elsif(clk'event and clk='1') then
if clkk='1' then
if(one1=9) then
one1<="0000";
if (ten1=9) then
ten1<="0000";
if (hu1=9) then
hu1<="0000";
if (th1=9) then
th1<="0000";
if ten_th1=9 then
ten_th1<="0000";
if hu_th1=9 then
hu_th1<="0000";
if million=9 then
million<="0000";
else
million<=million+1;
end if;
else
hu_th1<=hu_th1+1;
end if;
else
ten_th1<=ten_th1+1;
end if;
else
th1<=th1+1;
end if;
else
hu1<=hu1+1;
end if;
else
ten1<=ten1+1;
end if;
else
one1<=one1+1;
end if;
end if;
end if;
end process;
save:process(clkk)
begin
if(clkk'event and clkk ='0') then
if million>0 then
led_th<='0';
led_hu<='1';
led_ten<='1';
led_one<='1';
showth<=million;
showhu<=hu_th1;
showten<=ten_th1;
showone<=th1;
elsif hu_th1>0 then
showth<=hu_th1;
showhu<=ten_th1;
showten<=th1;
showone<=hu1;
led_th<='1';
led_hu<='0';
led_ten<='1';
led_one<='1';
elsif ten_th1>0 then
showth<=ten_th1;
showhu<=th1;
showten<=hu1;
showone<=ten1;
led_th<='1';
led_hu<='1';
led_ten<='0';
led_one<='1';
else
showth<=th1;
showhu<=hu1;
showten<=ten1;
showone<=one1;
led_th<='1';
led_hu<='1';
led_ten<='1';
led_one<='0';
end if;
end if;
end process;
end Behavioral;
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