choice.vhd

来自「采用VHDL语言写了一个函数发生器的程序。内含有各个模块」· VHDL 代码 · 共 60 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity choice is
    Port (key_route,reset,clk3200,clk_sin,clk_tri,clk_asl,clk_rectangular: in std_logic;
	       clk :out std_logic);
end choice;

architecture Behavioral of choice is

type state is (st1,st2);
signal current :state;

begin


process(key_route,clk3200)
variable cnt :integer range 5 downto 0 ;
begin
if reset='0' then
cnt:=1;
current<=st1;

elsif rising_edge(clk3200) then

 case current is
   when st1 =>if key_route='0' then current<=st2;
	           else
               case cnt is
				  when 1=>clk<=clk_sin;
              when 2=>clk<=clk_tri;
              when 3=>clk<=clk_asl;
				  when 4=>clk<=clk_rectangular;
				  
				  when others =>null;
				   
				  end case;
	            end if;  
   when st2 =>if key_route='1' then 
	           cnt:=cnt+1;
				  case cnt is
				  when 1=>clk<=clk_sin;current<=st1;
              when 2=>clk<=clk_tri;current<=st1;
              when 3=>clk<=clk_asl;current<=st1;
				  when 4=>clk<=clk_rectangular;current<=st1;
				  when 5=>cnt:=1;current<=st1;
				  when others =>null;
				   
				  end case;
				end if;
   when others=>null;
 end case;
 end if;

end process;

end Behavioral;