div.vhd

采用VHDL语言写了一个函数发生器的程序。内含有各个模块

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity div is
    Port (sysclk,reset,add,sub,step1,step10,step100,step1000 :in std_logic;
         
		
			 clkout:out std_logic;
			 clk3200,clk100:out std_logic);
end div;

architecture Behavioral of div is
signal clkk:std_logic;

type state is (st1,st2,st3);
signal current :state;
begin

process(sysclk,reset)
 variable count2: integer;
		variable clk0: std_logic;
		begin
		   if  reset='0' then
			 count2:=0;
			 clk0:='0';
			 elsif sysclk'event and sysclk='1' then
			  count2:=count2+1;
			  if count2=50 then
			  clk0:='1';
			  elsif count2=100then
			    count2:=0;
				 clk0:='0';
		     --end if;
			 end if;
			end if;

		clk100<=clk0;
end process;

process(sysclk,reset)
 variable count2: integer;
		variable clk0: std_logic;
		begin
		   if  reset='0' then
			 count2:=0;
			 clk0:='0';
			 elsif sysclk'event and sysclk='1' then
			  count2:=count2+1;
			  if count2=1600 then
			  clk0:='1';
			  elsif count2=3200then
			    count2:=0;
				 clk0:='0';
		     --end if;
			 end if;
			end if;
		clkk<=clk0;
		clk3200<=clk0;
end process;






process(sysclk,reset,clkk)
 variable count2,count3,count5: integer range 32000000 downto -2000 ;
		variable clk0: std_logic;
		begin
		if  reset='0' then
			 count2:=0;
			 clk0:='0';
			 count3:=1;
			 current<=st1;

		   elsif clkk'event and clkk='1' then
       case current is
		  when st1 =>if add='0' then current<=st2;
		             elsif sub='0' then current<=st3;
	                end if;  
        when st2 =>if add='1' then
		   if step1='0' then count3:=count3+1;current<=st1;
			elsif step10='0' then count3:=count3+10;current<=st1;
			elsif step100='0' then count3:=count3+100;current<=st1;
			elsif step1000='0' then count3:=count3+1000;current<=st1;
			end if;
			end if;
		  when st3 =>if sub='1' then
			if step1='0' then count3:=count3-1;current<=st1;
			elsif step10='0' then count3:=count3-10;current<=st1;
			elsif step100='0' then count3:=count3-100;current<=st1;
			elsif step1000='0' then count3:=count3-1000;current<=st1;
			end if;
			
			
			end if;
			when others =>null;
			end case;
			end if;

         count5:=count3*2;
		   if  reset='0' then
			 count2:=0;
			 clk0:='0';
			 count3:=1;
			 elsif sysclk'event and sysclk='1' then
			  count2:=count2+1;
			  if count2=count3 then
			  clk0:='1';
			  elsif count2=count5 then
			    count2:=0;
				 clk0:='0';
		     --end if;
			 end if;
			end if;
	
		clkout<=clk0;
	   end process ;




end Behavioral;