main.cpp

system C源码 一种替代verilog的语言

/*****************************************************************************

  The following code is derived, directly or indirectly, from the SystemC
  source code Copyright (c) 1996-2006 by all Contributors.
  All Rights reserved.

  The contents of this file are subject to the restrictions and limitations
  set forth in the SystemC Open Source License Version 2.4 (the "License");
  You may not use this file except in compliance with such restrictions and
  limitations. You may obtain instructions on how to receive a copy of the
  License at http://www.systemc.org/. Software distributed by Contributors
  under the License is distributed on an "AS IS" basis, WITHOUT WARRANTY OF
  ANY KIND, either express or implied. See the License for the specific
  language governing rights and limitations under the License.

 *****************************************************************************/

/*****************************************************************************
 
  main -- This is a simple CPU modeling using SystemC.
          Architecure defined by Martin Wang.
          You can initialize register by modifying file
          named register, and so is bios, and dacache.
 
  Original Author: Martin Wang, Synopsys, Inc.
 
 *****************************************************************************/
 
/*****************************************************************************
 
  MODIFICATION LOG - modifiers, enter your name, affiliation, date and
  changes you are making here.
 
      Name, Affiliation, Date:
  Description of Modification:
 
 *****************************************************************************/


#include "directive.h"
#include "systemc.h"
#include "bios.h"
#include "paging.h"
#include "icache.h"
#include "fetch.h"
#include "decode.h"
#include "exec.h"
#include "mmxu.h"
#include "floating.h"
#include "dcache.h"
#include "pic.h"
#include <climits>
#include <cstdlib>
#include <time.h>
//#include <sys/times.h>
#include <limits.h>

int sc_main(int ac, char *av[])
{

  // ************************ ICACHE ***********************************
  // ICACHE = ram_cs
  // ICACHE = ram_we
  // ICACHE = addr
  // ICACHE = ram_datain
  // ICACHE = ram_dataout
  // ICACHE = ld_valid = pid_valid
  // ICACHE = ld_data = pid_data
  sc_signal<bool>       icache_valid("ICACHE_VALID") ;

  // ************************ BIOS ***********************************
  sc_signal<bool>       ram_cs("RAM_CS") ;
  sc_signal<bool>       ram_we("RAM_WE") ;
  sc_signal<unsigned >    addr("Address") ;
  sc_signal<unsigned >    ram_datain("RAM_DATAIN") ;
  sc_signal<unsigned >    ram_dataout("RAM_DATAOUT") ;
  sc_signal<bool>       bios_valid("BIOS_VALID") ;
  const int delay_cycles = 2;

  // ************************ Paging ***********************************
  // Paging paging_din = ram_datain
  // Paging paging_csin = ram_cs
  // Paging paging_wein = ram_we
  // Paging logical_address = addr 
  sc_signal<unsigned >    icache_din("ICACHE_DIN") ;
  sc_signal<bool>       icache_validin("ICACHE_VALIDIN") ;
  sc_signal<bool>       icache_stall("ICACHE_STALL") ;
  sc_signal<unsigned >    paging_dout("PAGING_DOUT") ;
  sc_signal<bool>       paging_csout("PAGING_CSOUT") ;
  sc_signal<bool>       paging_weout("PAGING_WEOUT") ;
  sc_signal<unsigned >    physical_address("PHYSICAL_ADDRESS") ;
  // Paging dataout  = ram_dataout 
  // Paging data_valid = icache_valid
  // Paging stall_ifu = stall_fetch


  // ************************ Fetch ***********************************
  // IFU ramdata = ram_dataout
  sc_signal<unsigned >    branch_target_address("BRANCH_TARGET_ADDRESS") ;
  sc_signal<bool>       next_pc("NEXT_PC") ;
  sc_signal<bool>       branch_valid("BRANCH_VALID") ;
  sc_signal<bool>       stall_fetch("STALL_FETCH") ;
  sc_signal<bool>       pred_fetch("PRED_FETCH") ;
  // IFU ram_valid = bios_valid
  // IFU ram_cs = ram_cs
  // IFU ram_we = ram_we
  // IFU address = addr
  // IFU smc_instrction = ram_datain
  // IFU pred_branch_address = pred_branch_address
  // IFU pred_branch_valid = pred_branch_valid
  sc_signal<unsigned>   instruction("INSTRUCTION") ;
  sc_signal<bool>       instruction_valid("INSTRUCTION_VALID") ;
  sc_signal<unsigned >    program_counter("PROGRAM_COUNTER") ;
  sc_signal<bool>       branch_clear("BRANCH_CLEAR") ;
  sc_signal<bool>       pred_fetch_valid("PRED_FETCH_VALID") ;
  sc_signal<bool>       reset("RESET") ;

  // ************************ Branch ***********************************
  // BPU: fetch_inst = instruction
  // BPU: fetch_pc = program_counter
  // BPU: fetch_valid = instruction_valid
  // BPU: branch_inst_addr = branch_instruction_address
  // BPU: branch_target_address = branch_target_address
  // BPU: branch_valid = branch_valid
  sc_signal<unsigned >	pred_branch_address("PRED_BRANCH_ADDRESS");
  sc_signal<bool>       pred_branch_valid("PRED_BRANCH_VALID") ;
  sc_signal<bool>       pred_tellid("PRED_TELLID") ;
  sc_signal<unsigned>   pred_instruction("PRED_INSTRUCTION") ;
  sc_signal<bool>       pred_inst_valid("PRED_INST_VALID") ;
  sc_signal<unsigned >	pred_inst_pc("PRED_INST_PC");


  // ************************ Decode ***********************************
  // ID instruction = instruction
  // ID instruction = instruction_valid
  // ID destreg_write = out_valid
  // ID destreg_write_src = destout
  // ID clear_branch     = branch_clear 
  // ID pc = program_counter
  sc_signal<bool>       pred_on("PRED_ON") ;
  sc_signal<unsigned >	branch_instruction_address("BR_INSTRUCTION_ADDRESS");
  // ID alu_dataout = dout from EXEC 
  sc_signal<signed>     dram_dataout("DRAM_DATAOUT") ;
  sc_signal<bool>       dram_rd_valid("DRAM_RD_VALID") ;
  sc_signal<unsigned>   dram_write_src("DRAM_WRITE_SRC");
  // ID next_pc     = next_pc
  // ID branch_valid = branch_valid
  // ID branch_target_address = branch_target_address
  sc_signal<bool>       mem_access("MEM_ACCESS") ;
  sc_signal<unsigned >    mem_address("MEM_ADDRESS") ;
  sc_signal<int>        alu_op("ALU_OP") ;
  sc_signal<bool>       mem_write("MEM_WRITE") ;
  sc_signal<unsigned>   alu_src("ALU_SRC") ;
  sc_signal<bool>       reg_write("REG_WRITE") ;
  sc_signal<signed int> src_A("SRC_A") ;
  sc_signal<signed int> src_B("SRC_B") ;
  sc_signal<bool>       forward_A("FORWARD_A") ;
  sc_signal<bool>       forward_B("FORWARD_B") ;
  // ID stall_fetch = stall_fetch
  sc_signal<bool>       decode_valid("DECODE_VALID") ;
  sc_signal<bool>       float_valid("FLOAT_VALID") ;
  sc_signal<bool>       mmx_valid("MMX_VALID") ;
  sc_signal<bool>       pid_valid("PID_VALID") ;
  sc_signal<signed>     pid_data("PID_DATA") ;

  // ************************ DCACHE  ***********************************
  sc_signal<signed>       mmic_datain("MMIC_DATAIN") ;	/* DCU: datain 	*/
  sc_signal<unsigned>     mmic_statein("MMIC_STATEIN") ;/* DCU: statein */
  sc_signal<bool>     	  mmic_cs("MMIC_CS") ;		/* DCU: cs 	*/
  sc_signal<bool>     	  mmic_we("MMIC_WE") ;		/* DCU: we 	*/
  sc_signal<unsigned >      mmic_addr("MMIC_ADDR") ; /* DCU: addr	*/
  sc_signal<unsigned>     mmic_dest("MMIC_DEST") ;	/* DCU: dest 	*/
  sc_signal<unsigned>     mmic_destout("MMIC_DESTOUT") ;/* DCU: destout */
  sc_signal<signed>       mmic_dataout("MMIC_DATAOUT") ;/* DCU: dataout */
  sc_signal<bool>         mmic_out_valid("MMIC_OUT_VALID") ;/* DCU: out_valid*/
  sc_signal<unsigned>     mmic_stateout("MMIC_STATEOUT") ;/* DCU: stateout */

  // ************************ Execute ***********************************
  // EXEC in_valid = decode_valid
  sc_signal<bool>   	in_valid("IN_VALID") ;
  // EXEC opcode = alu_op
  sc_signal<bool>   	negate("NEGATE") ;