📄 decode.cpp
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case 0x09: // nand R1, R2, R3 printf("\t\t\tID: R%d=R%d(=%x) nand R%d(=%x)", regC_tmp, regA_tmp, srcA_tmp, regB_tmp, srcB_tmp); cout << " \n\t\t\t : at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; src_A.write(srcA_tmp); src_B.write(srcB_tmp); alu_src.write(regC_tmp); alu_op.write(7); decode_valid.write(true); wait(); decode_valid.write(false); wait(); break; case 0x0a: // and R1, R2, R3 printf("\t\t\tID: R%d=R%d(=%x) and R%d(=%x)", regC_tmp, regA_tmp, srcA_tmp, regB_tmp, srcB_tmp); cout << " \n\t\t\t : at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; src_A.write(srcA_tmp); src_B.write(srcB_tmp); alu_src.write(regC_tmp); alu_op.write(8); decode_valid.write(true); wait(); decode_valid.write(false); wait(); break; case 0x0b: // or R1, R2, R3 printf("\t\t\tID: R%d=R%d(=%x) or R%d(=%x)", regC_tmp, regA_tmp, srcA_tmp, regB_tmp, srcB_tmp); cout << " \n\t\t\t : at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; src_A.write(srcA_tmp); src_B.write(srcB_tmp); alu_src.write(regC_tmp); alu_op.write(9); decode_valid.write(true); wait(); decode_valid.write(false); wait(); break; case 0x0c: // xor R1, R2, R3 printf("\t\t\tID: R%d=R%d(=%x) xor R%d(=%x)", regC_tmp, regA_tmp, srcA_tmp, regB_tmp, srcB_tmp); cout << " \n\t\t\t : at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; src_A.write(srcA_tmp); src_B.write(srcB_tmp); alu_src.write(regC_tmp); alu_op.write(10); decode_valid.write(true); wait(); decode_valid.write(false); wait(); break; case 0x0d: // NOT R1, R2 printf("\t\t\tID: R%d= NOT R%d(=%x)", regC_tmp, regA_tmp, srcA_tmp); cout << " \n\t\t\t : at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; src_A.write(srcA_tmp); src_B.write(0); alu_src.write(regC_tmp); alu_op.write(11); decode_valid.write(true); wait(); decode_valid.write(false); wait(); break; case 0x0e: // modulo R1 = R2 mod R3 printf("\t\t\tID: R%d= R%d(=%x) mod R%d(=%x)", regC_tmp, regA_tmp, srcA_tmp, regB_tmp, srcB_tmp); cout << " \n\t\t\t : at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; src_A.write(srcA_tmp); src_B.write(srcB_tmp); alu_src.write(regC_tmp); alu_op.write(14); decode_valid.write(true); wait(); decode_valid.write(false); wait(); break; case 0x4d: // lw R1, R2, offset printf("\t\t\tID: R%d<=mem[R%d=(%d)+%d]", regC_tmp, regA_tmp, srcA_tmp, offset_tmp); cout << " \n\t\t\t : at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; mem_access.write(true); mem_write.write(false); alu_src.write(regC_tmp); offset_tmp = offset_tmp + srcA_tmp; mem_address.write(offset_tmp); wait(); mem_access.write(false); wait(); break; case 0x4e: // sw R1, R2, offset printf("\t\t\tID: R%d=>mem[R%d(=%d) + %d]", regC_tmp, regA_tmp, srcA_tmp, offset_tmp); cout << " \n\t\t\t : at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; mem_access.write(true); mem_write.write(true); offset_tmp = offset_tmp + srcA_tmp; mem_address.write(offset_tmp); wait(); mem_access.write(false); mem_write.write(false); wait(); break; case 0x0f: // mov R1, R2 printf("\t\t\tID: R%d=R%d(=%d)", regC_tmp, regA_tmp, srcA_tmp); cout << " \n\t\t\t : at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; src_A.write(srcA_tmp); src_B.write(0); alu_src.write(regC_tmp); alu_op.write(3); decode_valid.write(true); wait(); decode_valid.write(false); wait(); break; case 0x10: // beq R1, R2, label src_A.write(0); src_B.write(0); alu_src.write(0); alu_op.write(3); decode_valid.write(true); if (srcC_tmp == srcA_tmp) { branch_target_address.write(pc_reg + label_tmp); br_instruction_address.write(instr_tmp); branch_valid.write(true); printf("\t\t\tID: beq R%d(=%d), R%d(=%d), pc+=(%d).\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp, label_tmp); } else { printf("\t\t\tID: beq R%d(=%d) != R%d(=%d),pc++.\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp); } cout << "\t\t\tID: at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; wait(); branch_target_address.write(pc_reg + 1); decode_valid.write(false); wait(); break; case 0x11: // bne R1, R2, label src_A.write(0); src_B.write(0); alu_src.write(0); alu_op.write(3); decode_valid.write(true); if (srcC_tmp != srcA_tmp) { branch_target_address.write(pc_reg + label_tmp); br_instruction_address.write(instr_tmp); branch_valid.write(true); printf("\t\t\tID: bne R%d(=%d), R%d(=%d), pc+=(%d).\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp, label_tmp); } else { printf("\t\t\tID: bne R%d(=%d) = R%d(=%d),pc++.\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp); } cout << "\t\t\tID: at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; wait(); branch_target_address.write(pc_reg + 1); decode_valid.write(false); wait(); break; case 0x12: // bgt R1, R2, label src_A.write(0); src_B.write(0); alu_src.write(0); alu_op.write(3); decode_valid.write(true); if (srcC_tmp > srcA_tmp) { branch_target_address.write(pc_reg + label_tmp); br_instruction_address.write(instr_tmp); branch_valid.write(true); printf("\t\t\tID: bgt R%d(=%d)>R%d(=%d), pc+=(%d).\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp, label_tmp); } else { printf("\t\t\tID: bgt R%d(=%d) <= R%d(=%d),pc++.\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp); } cout << "\t\t\tID: at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; wait(); branch_target_address.write(pc_reg + 1); decode_valid.write(false); wait(); break; case 0x13: // bge R1, R2, label src_A.write(0); src_B.write(0); alu_src.write(0); alu_op.write(3); decode_valid.write(true); if (srcC_tmp >= srcA_tmp) { branch_target_address.write(pc_reg + label_tmp); br_instruction_address.write(instr_tmp); branch_valid.write(true); printf("\t\t\tID: bge R%d(=%d)>=R%d(=%d), pc+=(%d).\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp, label_tmp); } else { printf("\t\t\tID: bge R%d(=%d) < R%d(=%d),pc++.\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp); } cout << "\t\t\tID: at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; wait(); branch_target_address.write(pc_reg + 1); decode_valid.write(false); wait(); break; case 0x14: // blt R1, R2, label src_A.write(0); src_B.write(0); alu_src.write(0); alu_op.write(3); decode_valid.write(true); if (srcC_tmp < srcA_tmp) { branch_target_address.write(pc_reg + label_tmp); br_instruction_address.write(instr_tmp); branch_valid.write(true); printf("\t\t\tID: blt R%d(=%d)<R%d(=%d), pc+=(%d).\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp, label_tmp); } else { printf("\t\t\tID: blt R%d(=%d) >= R%d(=%d), pc++.\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp); } cout << "\t\t\tID: at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; wait(); branch_target_address.write(pc_reg + 1); decode_valid.write(false); wait(); break; case 0x15: // ble R1, R2, label src_A.write(0); src_B.write(0); alu_src.write(0); alu_op.write(3); decode_valid.write(true); if (srcC_tmp <= srcA_tmp) { branch_target_address.write(pc_reg + label_tmp); br_instruction_address.write(instr_tmp); branch_valid.write(true); printf("\t\t\tID: ble R%d(=%d)<=R%d(=%d), pc+=(%d).\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp, label_tmp); } else { printf("\t\t\tID: ble R%d(=%d)>R%d(=%d), pc++.\n", regC_tmp, srcC_tmp, regA_tmp, srcA_tmp); } cout << "\t\t\tID: at CSIM " << sc_time_stamp() << endl; cout << "\t\t\t-------------------------------" << endl; wait(); branch_target_address.write(pc_reg + 1); decode_valid.write(false); wait(); break;⌨️ 快捷键说明
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