readme

system C源码 一种替代verilog的语言

Here the blocking master reads a block of data, performs the same 
arithmetic operations on the data as the non-blocking master, and 
writes it back to memory as a block. This master has a lower 
priority than the non-blocking master, to enable interrupts of 
higher prioritized requests during a burst mode transaction. 

2.2.3 Direct Masters

SC_MODULE(simple_bus_master_direct)
   {
     // ports
     sc_clk_in clock;
     sc_port<simple_bus_direct_if> bus_port;

     // constructor
     simple_bus_master_direct(sc_module_name name,
                              ...)
     ...
   };

The direct master monitors some memory locations at distinct time intervals 
and prints them on the screen. 



---------------------------------------------------------------------------
      +---------+   +---------+   +---------+
      | master  |   | master  |   | master  |
  +-->|   #1    |-->|   #2    |-->|   #3    |
  |   +-- [*]---+   +---[*]---+   +---[*]---+
  |        |             |             |
  |        +-------------+-------------+
  |                      |                          
  |      /--------------(.)--------------\
  +->[*]/        simple_bus               \          +----------+
  |     \                                 /[*]----(.)| arbiter  |
  |      \--------------[*]--------------/           +----------+
  |                     | |                
  |                 ____/ \____
clock              /           \
  |                |           |
  |            +--(.)--+   +--(.)--+         legend:
  |            | slave |   | slave |         [*] : port
  +----------->|  #1   |   |  #2   |         (.) : interface
               +-------+   +-------+

  Figure 1: the simple_bus with three masters, two slaves and the arbiter.
---------------------------------------------------------------------------

2.3 The Test 'Schematic'

The testbench contains a bus with arbiter, three different masters,
each supporting a specific bus interface, and two slaves modeling a
memory without wait states (fast memory), and a memory with wait
states (slow memory). The testbench is available as the hierarchical
module simple_bus_test. 

2.3.1 Construction

The testbench contains the clock channel 'C1' and the different
instances. These instances are allocated in the simple_bus_test
constructor and are configured by means of constructor arguments. The
default argument is the name of the module, but for the masters and
the slaves additional parameters must be specified.

The memories cover the byte address range [0:ff] where the first half of
the address space ([0:7f])is covered by a fast memory, and the second
half of the address space ([0x80:0xff]) is covered by a slow memory
with 1 wait state:

- simple_bus_fast_mem("mem_fast", // name
		      0x00,       // start_address
                      0x7f);      // end_address 
- simple_bus_slow_mem("mem_slow", // name
                      0x80,       // start_address
                      0xff,       // end_address
                      1);         // number of wait states

For the masters, the unique priority must be defined during
construction time, except for the direct master. The priority is not
directly checked during construction, but only during run time by the
arbiter. If during the same cycle two or more request are issued with
the same priority, the simulation will abort after issuing an error
message:

- simple_bus_master_blocking("master_b", 4, ...);      // unique_priority = 4
- simple_bus_master_non_blocking("master_nb", 3, ...); // unique_priority = 3

2.3.2 Simulation

The simple_bus_test instance is instantiated in the sc_main routine
and the simulation is started by the sc_start(10000) statement.

This is coded in the simple_bus_main.cpp file. 

2.4 Runtime Behavior

The three different masters issue bus requests independently of each other. 
A single request, but also multiple requests at the same cycle are possible. 
Each master has its own behavior. 

2.4.1 Direct Master

The direct master serves as a monitor that reads at certain time
intervals four adjacent memory locations and prints them on the output
stream, using the direct bus interface.

With m_address = 0x78, and m_timeout = 100, the direct master performs:

  while (true)
    {
      bus_port->direct_read(&mydata[0], m_address);
      bus_port->direct_read(&mydata[1], m_address+4);
      bus_port->direct_read(&mydata[2], m_address+8);
      bus_port->direct_read(&mydata[3], m_address+12);

      if (m_verbose)
	sb_fprintf(stdout, "%f %s : mem[%x:%x] = (%x, %x, %x, %x)\n",
		   sc_time_stamp(), name(), m_address, m_address+15, 
		   mydata[0], mydata[1], mydata[2], mydata[3]);

      wait(m_timeout, SC_NS);
    }

The parameters m_address and m_timeout are configurable by means of
constructor arguments. Printing of the memory locations is enabled
when m_verbose is set. Also that is configurable with a constructor
argument.

2.4.2 Non-Blocking Master

The non-blocking master reads a word 'data' at byte address 'addr' from 
memory, using the non-blocking bus interface function and checks whether 
the operation is successful. 'data' is modified a little bit and written 
to the same 'addr' in memory. After 'm_timeout' the next iteration is
started. Each iteration, 'addr' is set to the next word address.

With addr = 0x38, and m_timeout = 20, the non-blocking master
performs: 

  wait(); // ... for the next rising clock edge
  while (true)
    {
      bus_port->read(m_unique_priority, &mydata, addr, m_lock);
      while ((bus_port->get_status(m_unique_priority) != SIMPLE_BUS_OK) &&
	     (bus_port->get_status(m_unique_priority) != SIMPLE_BUS_ERROR))
	wait();
      if (bus_port->get_status(m_unique_priority) == SIMPLE_BUS_ERROR)
	sb_fprintf(stdout, "%f %s : ERROR cannot read from %x\n",
		   sc_time_stamp(), name(), addr);

      mydata += cnt;
      cnt++;

      bus_port->write(m_unique_priority, &mydata, addr, m_lock);
      while ((bus_port->get_status(m_unique_priority) != SIMPLE_BUS_OK) &&
	     (bus_port->get_status(m_unique_priority) != SIMPLE_BUS_ERROR))
	wait();
      if (bus_port->get_status(m_unique_priority) == SIMPLE_BUS_ERROR)
	sb_fprintf(stdout, "%f %s : ERROR cannot write to %x\n",
		   sc_time_stamp(), name(), addr);
 
      wait(m_timeout, SC_NS);
      wait(); // ... for the next rising clock edge

      addr+=4; // next word (byte addressing)
      if (addr > (m_start_address+0x80)) {
	addr = m_start_address; cnt = 0; 
      }
    }

Initially, all bus interface function calls are not locked. The lock
can be set by means of a constructor argument.

2.4.3 Blocking Master

The blocking master reads a block of 'data' words at byte 'addr' and of 
word length 0x10 from memory, performs some arithmetic calculations on them, 
that takes 0x10 wait states, and writes the block of 'data' back to memory
at 'addr'. Then it pauses 'm_timeout' nanoseconds before the next 
iteration starts.

With m_address = 0x4c and m_timeout = 300, the blocking master performs:

  while (true)
    {
      wait(); // ... for the next rising clock edge
      status = bus_port->burst_read(m_unique_priority, mydata, 
				    m_address, mylength, m_lock);
      if (status == SIMPLE_BUS_ERROR)
	sb_fprintf(stdout, "%f %s : blocking-read failed at address %x\n",
		   sc_time_stamp(), name(), m_address);

      for (i = 0; i < mylength; ++i)
	{
	  mydata[i] += i;
	  wait();
	}

      status = bus_port->burst_write(m_unique_priority, mydata, 
				     m_address, mylength, m_lock);
      if (status == SIMPLE_BUS_ERROR)
	sb_fprintf(stdout, "%f %s : blocking-write failed at address %x\n", 
		   sc_time_stamp(), name(), m_address);

      wait(m_timeout, SC_NS);
    }

Initially, all bus interface function calls are not locked. The lock
can be set by means of a constructor argument.

2.5 Running

The runtime behavior is best be monitored by inspection of the
collection of pending requests at the arbiter, and the identification
of the selected request. The arbiter is called each cycle when there
are one or multiple requests pending. A burst request is split up in
separate requests for each slave action.

Let R[p](-) be a request R of priority 'p' without a lock, and let
R[p](+) be the same request, but now with a lock. For each cycle the
list of requests is shown with the one selected. 

- R[3](-)  
// single request, is selected

- R[3](-) R[4](-)  
// two requests, R[3](-) is selected according priority

- R[3](-) R[3](-) R[4](-) 
// error: two requests with the same priority. Abort, end of simulation!

It does not matter whether the request is part of a burst-request or
just a non-blocking request. Each cycle the most appropriate (partial)
request is selected. When R[4] is part of a burst-request, then it can
be interrupted by R[3], due to a higher priority. 

When the lock is set, the behavior is slightly different. Not for the
first selection of a request but for the next one, issued by the same
master. 

1: R[3](+)
2: R[3](+)
// single request for cycle 1 and 2, no conflicts

1: R[3](+)
2: R[4](+)
// locked request at cycle 1, but is not followed by a next request. 
// R[4] is selected at cycle 2.

1: R[4](+)
2: R[3](-) R[4](+)
// locked request at cycle 1: selected. Request is issued again at
// cycle 2, so the lock is kept and the request with a higher priority
// must wait.

1: R[4](+)
2: R[3](+) R[4](+)
// locked request at cycle 1: selected. Request is issued again at
// cycle 2, so R[4] is selected in cycle 2. R[3] must wait, regardless
// the higher priority and its lock.


3. Files

ChangeLog
LEGAL
Makefile.gcc
Makefile.hp
Makefile.linux
Makefile.srcs
Makefile.sun
README
SLIDES.pdf
simple_bus.cpp
simple_bus.golden
simple_bus.h
simple_bus_arbiter.cpp
simple_bus_arbiter.h
simple_bus_arbiter_if.h
simple_bus_blocking_if.h
simple_bus_direct_if.h
simple_bus_fast_mem.h
simple_bus_main.cpp
simple_bus_master_blocking.cpp
simple_bus_master_blocking.h
simple_bus_master_direct.cpp
simple_bus_master_direct.h
simple_bus_master_non_blocking.cpp
simple_bus_master_non_blocking.h
simple_bus_non_blocking_if.h
simple_bus_request.h
simple_bus_slave_if.h
simple_bus_slow_mem.h
simple_bus_test.h
simple_bus_tools.cpp
simple_bus_types.cpp
simple_bus_types.h