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system C源码 一种替代verilog的语言

1.3 Arbiter

To the bus more than one master can be connected. Each master is
independent of the others, so each master can issue a bus request at
any time. When at a given cycle one or more requests are made for the
bus, these requests are collected and passed to an arbiter. Out of
this collection the most suitable request is selected; the other
requests are kept in the request state. The arbiter is connected to
the bus by a dedicated interface, and is called with one or more
requests in the collection:

simple_bus_request *arbitrate(const simple_bus_request_vec &Q);

The arbiter selects the most appropriate request according the
following rules: 

1. If the current request is a locked burst request, then it is always 
   selected.
2. If the last request had its lock flag set and is again
   'requested', this request is selected from the collection Q and
   returned, otherwise:
3. the request with the highest priority (i.e. lowest number) is
   selected from the collection Q and returned.

The arbiter checks whether all the priorities of the requests are
unique. If that is not the case, the arbiter will produce an error
message and abort execution.

The arbiter is called whenever the last master request is fully
processed by the bus, and when there are one or more new requests made
by the set of masters.

NOTE: The highest priority is specified by the lowest numerical value
of the unique_priority parameter. 

1.4 Timing

A bus transfer is initiated by a master request. Each master is
sensitive to the rising clock edge where it can call a bus interface
function.

1.4.1 Blocking Request

At the rising clock edge, masters can issue a bus request. The bus
interface function registers the request in a request form. The status
of the request becomes SIMPLE_BUS_REQUEST. (The interface function does
not terminate but waits until the status of the bus is either
SIMPLE_BUS_OK or SIMPLE_BUS_ERROR, and this status is returned at the
first rising clock edge after the request is fully completed.)

At the next falling clock edge after the request is issued, the bus
handles the requests. Since now there is one (or more) request made,
the arbiter is called to determine the most suitable request. The
status of this request is set to SIMPLE_BUS_WAIT. This request is then
executed.

For each data transfer to be made, ranging from start_address to
start_address + length - 1, the current address is obtained and the
corresponding slave is selected.  If there is no slave to be found,
the status of the request is set to SIMPLE_BUS_ERROR.

The master request is transformed into single slave requests, and one
by one these requests are made to the slave. When the status of the
slave is SIMPLE_BUS_OK after the call is made, then the transfer of a
single data element has succeeded, the current address of the master
request is incremented. If the current address is beyond the last
to-be-addressed data element, the status of the request is set to
SIMPLE_BUS_OK and the event is notified, for which the bus interface
function that issued the request is waiting.

If there are more data elements to be sent to the slave interface, the
status of the request remains SIMPLE_BUS_WAIT. At the next falling
clock edge the bus process continues with the data transfer to the
slave until all data elements are done.

If a slave encounters an error, the status of the request is set to
SIMPLE_BUS_ERROR and the event is notified, for which the
bus interface function that issued the request is waiting.

The bus interface function does not actually wait until the status of
the call becomes SIMPLE_BUS_OK or SIMPLE_BUS_ERROR, but waits for an
event coming from the bus process indicating that the transfer is
completed. This event comes at the falling clock edge. An additional
wait for the next rising clock edge must be issued in order
to synchronize:

simple_bus_status burst_read(...) {
  // register request
  ...
  wait(request->transfer_done);
  wait(clock->posedge_event());
  return get_status(priority);
}

1.4.2 Non-Blocking Request

A non-blocking master request is done at a rising clock edge. The
request is registered by the bus by filling in the request form and
the status of the request is set to SIMPLE_BUS_REQUEST. The
non-blocking function returns. The status of the request changes as
soon as the bus handles the request, and that happens at a falling
clock edge.

Now the master must check for the status of the request until the
status is either SIMPLE_BUS_OK or SIMPLE_BUS_ERROR. Only the bus
process can change the status of the request once the request is
made. And that happens only at a falling clock edge. The same
procedure is now followed for transferring one single data element
through the bus as is described for the blocking interface request
functions.

1.4.3 Direct Request

A direct interface request from a master does not follow the bus
protocol, but is handled instantaneously. Once the request is issued
by a master, it is directly transformed into the corresponding direct
slave interface function call. The only action performed by the bus is
the selection of the slave according to the address argument of the
direct interface function call.

At the slave this direct request is also processed immediately without
honoring the wait states of the slave. The function will return and
its return value is either true if the given address could be read
and/or written, or is false if that is not the case.

The return value of the direct request of the bus interface function
call is the same as for the slave side of the interface, only when the
address parameter could not be mapped to a slave, it will also return
false.

1.5 Interfaces Used

class simple_bus_direct_if 
   : virtual public sc_interface 
   {...};

class simple_bus_non_blocking_if 
   : virtual public sc_interface 
   {...};

class simple_bus_blocking_if 
   : virtual public sc_interface 
   {...};

class simple_bus_arbiter_if 
   : virtual public sc_interface 
   {...};

class simple_bus_slave_if 
   : public simple_bus_direct_if
   {...};


1.5.1 Bus

The bus is a hierarchical channel, providing the three different
bus interfaces, and containing a clock port, an arbiter port and a
(multi-)port for connecting one or more slaves. 

class simple_bus
   : public simple_bus_direct_if
   , public simple_bus_non_blocking_if
   , public_simple_bus_blocking_if
   , public sc_module
   {
      sc_clk_in clock;
      sc_port<simple_bus_slave_if, 0> slave_port;
      sc_port<simple_bus_arbiter_if> arbiter_port;
      ...
   };

The implementation of the main process of the bus is a method process,
using dynamic sensitivity for 'communicating' with the bus interface
functions. The communication towards the slave interface does not use
dynamic sensitivity.

1.5.2 Arbiter

The arbiter is a hierarchical channel that provides the
simple_bus_arbiter_if interface.

class simple_bus_arbiter
   : public simple_bus_arbiter_if
   , public sc_module
   {...};


2. The Testbench

The testbench consists of an instantiation of the simple_bus with an
arbiter, three masters and two slaves. Both slaves model a random
access memory where the first memory does not have a wait state while
the second memory has (some). The testbench contains three masters
where each master issues only requests of a particular interface, like
only issuing blocking interface function calls, only non-blocking
interface function calls or only direct interface function calls.

2.1 Slaves

Two kinds of memories are to be modeled: one without wait states and
one with a configurable number of wait states. 

2.1.1 Fast Memory Slaves

The fast memory slave has no wait states and no clock port. It reacts
immediately to the bus request and sets the status accordingly. 

class simple_bus_fast_mem
   : public simple_bus_slave_if
   , public sc_module
   {
   public:
      // no ports

      // constructor
      simple_bus_fast_mem(sc_module_name name,
                          unsigned int start_address,
                          unsigned int end_address) 
      ...
      // interface methods
      ...
   };

The start_address points to the first byte of the first word in the 
memory of this slave and is a word aligned address, i.e. it has to 
be a multiple of 4. The end_address points to the last byte of the 
last word in the memory area of this slave, i.e. to address 
(start_address + storage_size_in_words * 4 - 1).

2.1.2 Slow Memory Slaves

The slow memory slave has a configurable number of wait states
(constructor argument), and contains a clock port. Once a request is
made, the status is set to SIMPLE_BUS_WAIT, and a counter is set. Each
rising clock edge this counter is decremented and checked, and if it
becomes zero, the status is set to SIMPLE_BUS_OK. This status is
picked up by the bus at the next falling clock edge.

class simple_bus_slow_mem
   : public simple_bus_slave_if
   , public sc_module
   {
   public:
      sc_clk_in clock;

      // constructor
      simple_bus_slow_mem(sc_module_name name,
                          unsigned int start_address,
                          unsigned int end_address, 
                          unsigned int nr_wait_states)
      ...
      // interface methods
      ...
   };

The start_address points to the first byte of the first word in the 
memory of this slave and is a word aligned address, i.e. it has to 
be a multiple of 4. The end_address points to the last byte of the 
last word in the memory area of this slave, i.e. to address 
(start_address + storage_size_in_words * 4 - 1).

2.2 Masters

For the testbench three masters are defined, each using one bus
interface: blocking, non-blocking or direct. The main_action of each
master is a thread process.

2.2.1 Non-Blocking Masters

SC_MODULE(simple_bus_master_non_blocking)
   {
     // ports
     sc_clk_in clock;
     sc_port<simple_bus_non_blocking_if> bus_port;

     // constructor
     simple_bus_master_non_blocking(sc_module_name name,
                                    unsigned int unique_priority,
                                    ...)
     ...
   };

In this example the non-blocking master reads data from a memory 
location, performs an arithmetic operation on this data and writes 
it back to memory. This happens in a loop so that the memory 
locations are at least changed each loop iteration.

2.2.2 Blocking Masters

SC_MODULE(simple_bus_master_blocking)
   {
     // ports
     sc_clk_in clock;
     sc_port<simple_bus_blocking_if> bus_port;

     // constructor
     simple_bus_master_blocking(sc_module_name name, 
                                unsigned int unique_priority,
                                ...)
     ...
   };