sccahdlcdrv.h

支持VXWORKES操作系统下MPC860系列处理器地异步HDLC驱动

/* SccAhdlcdrv.h  - Asynchronous  HDLC device driver for mpc852 */ 

#ifndef	__INCsccahdlcDrvh
#define	__INCsccahdlcDrvh

#ifdef __cplusplus
extern "C" {
#endif

#include "vxWorks.h"
#include "sioLib.h"
#include "drv/multi/ppc860Cpm.h"
#include "drv/multi/ppc860Siu.h"
#include "iosLib.h"
#include "semLib.h"
#include "selectLib.h"

#if 0
typedef struct ahdlcResource	/* AHDLC_RESOURCE */
    {

    } AHDLC_RESOURCE;
#endif

/*#define        M_DEBUG */
/*#define  AHDLC_CRC16*/

typedef struct 			/* AHDLC_DEV */
    {

     DEV_HDR	devHdr;
     BOOL	created;        /* TRUE if this device has been created */
	 
    UINT32 RegMEMBase;
    INT32	instance;	/* instance number */
    INT32	intCnt;         /* interrupt count */
    INT32	retryCnt;       /* retry count */
    INT32	timeout;        /* timeout second for syncSem */
    INT32	intVector;	/* interrupt vector number */
    INT32	intLevel;       /* interrupt level */
    INT32	charsPrinted;	/* total characters printed */
 
    BOOL	autofeed;       /* TRUE if enable autofeed */
    BOOL	inservice;      /* TRUE if interrupt in service */
    } AHDLC_DEV;

typedef struct 			/* AHDLC_DRV */
    {
   
    } AHDLC_DRV;


#define		SCC_NUM		1            /* max AHDLC number */

/*
缓冲区数据结构定义
*/
#define SCC_BD_SZ					8
#define AHDLC_MAX_BUF_LEN				256				/* 每个缓冲区的长度 */
#define AHDLC_MAX_PKT_LEN					(AHDLC_MAX_BUF_LEN - 4)		
#define SCC_AHDL_FRAME_SIZE				AHDLC_MAX_BUF_LEN				/* buffer size 128 bytes */
#define SCC_AHDLC_MRBLR			         SCC_AHDL_FRAME_SIZE               /* maximum length of receive frame include CRC ,used for CPM para */


#define SCC4_AHDLC_BD_BASE	0x2C00		/* SCC4 BD base address from IMMR  , Address from 0x2c00 to 0x2dff  */
#define SCC_NUM_TBD				2						/* number of transmite BDs */
#define SCC_NUM_RBD				4					/* number of receive BDs */


#define SCC_AHDLC_RECV_BUF_NUM	4





enum SCC_NO
{
	SCC4 = 0,
	SCC3
};

#define MPC860_DPR_SCC3(base)  (CAST(VUINT32 *) ((base) + MPC860_REGB_OFFSET \
														+ 0x1e00))
#define MPC860_DPR_SCC4(base)  (CAST(VUINT32 *) ((base) + MPC860_REGB_OFFSET \
														+ 0x1f00))

typedef struct  
{
	VUINT8			status;			/* 缓冲区状态，0--空闲，1--被占用 */
	UINT8			linknum;		/* 链路号 */
	UINT16			len;			/* 消息长度 消息长度不大于(AHDLC_MAX_BUF_LEN - 2)字节 */
	UINT8			body[AHDLC_MAX_PKT_LEN];
#ifdef AHDLC_CRC16
	UINT8			needcrc;
#else
	UINT8			ret0;
#endif /* end of  AHDLC_CRC16*/ 
	UINT8			ret1;
	UINT8			ret2;
	UINT8			ret3;
}BUFM_BUF;


typedef struct {
	SCC_PARAM			param;          /* SCC parameters */
	volatile INT32		res1;			/* 0x30 reserved */
	volatile INT32		c_mask;			/* 0x34 CRC constant. Initialize with 0x0000_F0B8. */
	volatile INT32		c_pres;			/* 0x38 CRC preset. Initialize with 0x0000_FFFF. */
	volatile INT16		bof; 			/* 0x3c Beginning-of-flag-character. Initialize to PPP-0x7E, IrLAP - 0xC0. */
	volatile INT16		eof;		      		/* 0x3e End-of-flag character. Initialize to PPP-0x7E, IrLAP-0xC1. */
	volatile INT16		esc;		 		/* 0x40 Control escape character. Initialize to 0x7D for both PPP and IrLAP.*/
	volatile INT16		res2;			/* 0x42  */
	volatile INT16		res3;			/* 0x44  */
	volatile INT16		zero;			/* 0x46 Clear this field. */
	volatile INT16		res4	;		/* 0x48  */
	volatile INT16		rfthr;			/* 0x4a Received frames threshold. Number of Rx frames needed to trigger SCCE[RXF] */
	volatile INT32		res5;			/* 0x4c  */
	volatile INT32		txctl_tbl;		/* 0x50 Control character tables.*/
	volatile INT32  	rxctl_tbl;		/* 0x54 Control character tables.*/
	volatile INT16		nof;				/* 0x58 Number of opening flags to be sent at the beginning of a frame. A value of n
										     corresponds to n+1 flags. */
	volatile INT16		res6;			/* 0x5a */

}SCC_AHDLC_PARAM;

enum SCC_RESULT_CODE
{
	_eSCCSuccess,			
	_eSCCGeneralErr,
	_eSCCDevCreateErr,
	_eSCCDevWrErr,
	_eSCCMemAssErr,
	_eSCCDevInitErr,
	_eSCCBdInitErr,
	_eSCCPortSetErr,
	_eSCCClkSetErr,
	_eSCCCpcrCmdExecErr,
	_eSCCWrSizeErr,
	_eSCCWrNoBdErr,
	_eSCCNoUsrMemory,
	_eSCCNoCachMemory,
	_eSCCNoDriver	
};



typedef struct			/* SCC_AHDLC_BD */
{
	volatile UINT16		statusMode;
	UINT16				dataLength;
	unsigned char *		dataPointer;
}SCC_AHDLC_BD;

typedef struct {

  int sent;
  int recive; 
  int  pnumCrcec;	/* CRC error counter */
  int 	 rx_break ;
  int   rx_frame_close ;
  int   rx_ab;
  int   rxov;
  int    elseerr;
  int   total;	
}SCC_AHDLC_STATISTIC;

typedef struct			/* scc_ahdlc_dev */
{
       DEV_HDR    devHdr;		/* for adding to device table */
	 SCC_AHDLC_STATISTIC	statistics;  

	int					immrVal;

	unsigned char *		ptran_buf_malloc_address;
	unsigned char *		ptran_buf_base;		/* transmite buffer base address. */
	unsigned char *		precv_buf_malloc_address;
	unsigned char *		precv_buf_base;		/* receive buffer base address. */

	volatile SCC_AHDLC_PARAM *	pscc_params;			/* scc hdlc parameters */

	volatile SCC_REG	*			pscc_regs;			/* scc registers */

	INT16				transBD_base;
	SCC_AHDLC_BD *		ptran_BD;			/* transmite BDs */
	int					current_tBD;		/* current processed BD */
	
	INT16				recvBD_base;
	SCC_AHDLC_BD *		precv_BD;			/* transmite BDs */
	int					current_rBD;		/* current processed BD */

	BUFM_BUF *			usr_recv_buf ;	/* store recved pkt */
	int					rbuf_wptr;
	int					rbuf_rptr;
	BOOL                          opened;
	volatile int  * 				      pBaud;
      

 	SEL_WAKEUP_LIST 	   selWakeupkist;
	
	
	BOOL 	ready_to_read;
	BOOL 	ready_to_write;
	
	SEM_ID   writeSem;        /*  trans proc semaphore */
	SEM_ID   readSem;        /*  recv wait  semaphore */

}SCC_AHDLC_DEV;



#define CRC_16_MASK		0x0000f0b8


#define CRC_16_PRES		0x0000ffff





#define SCC_CPCR_DELAY			0x10000

/* CPCR */
#define CPCR_OPCODE_INITTR_PARA		0x0000
#define CPCR_OPCODE_INITRX_PARA		0x0100
#define CPCR_OPCODE_INITTX_PARA		0x0200
#define CPCR_OPCODE_EHM				0x0300
#define CPCR_OPCODE_STOPTX			0x0400
#define CPCR_OPCODE_GSTOPTX			0x0500
#define CPCR_OPCODE_RESTARTTX		0x0600
#define CPCR_OPCODE_CLOSERXBD		0x0700

#define CPCR_CHNUM_SCC3				0x0080
#define CPCR_CHNUM_SCC4				0x00c0


/*SCCE*/
#define SCC_AHDLC_SCCE_GLR			0x1000
#define SCC_AHDLC_SCCE_GLT			0x0800
#define SCC_AHDLC_SCCE_IDL			0x0100
#define SCC_AHDLC_SCCE_TXE			0x0010
#define SCC_AHDLC_SCCE_BRKE		0x0040
#define SCC_AHDLC_SCCE_BRKS		0x0020
#define SCC_AHDLC_SCCE_RXF			0x0008
#define SCC_AHDLC_SCCE_BSY			0x0004
#define SCC_AHDLC_SCCE_TXB			0x0002
#define SCC_AHDLC_SCCE_RXB			0x0001

/*GSMR_L*/
#define SCC_GSMRL_AHDLC			0x00000006		/*AHDLC mode */
#define SCC_GSMRL_HDLC				0x00000000		/*HDLC mode */
#define SCC_GSMRL_DIAG_NO			0x00000000		/* DIAGNOSTIC MODE: normal operation */
#define SCC_GSMRL_DIAG_LOOP			0x00000040		/* Diagnostic mode: local loop back mode */

/* PSMR */
#define HDLC_PSMR_NOF_MASK		0xf000			/*NOF--number of flags */
#define AHDLC_PSMR_FLC  				0x8000			/* Flow control,0 Normal operation.1 Asynchronous flow control.*/
#define AHDLC_PSMR_CHLN             		0x3000            	/* Character length. CHLN must be set to 0b11 */

/* CIMR CICR */
#define CIMR_SCC3					0x10000000		/* SCC3 interrupt mask */
#define CIMR_SCC4					0x08000000		/* SCC4 interrupt mask */


/* Receive BD status bits 16-bit value */

#define AHDLC_BD_RX_EMPTY_BIT			0x8000	/* buffer is empty */
#define AHDLC_BD_RX_WRAP_BIT			0x2000	/* last BD in chain */
#define AHDLC_BD_RX_INTERRUPT_BIT		0x1000	/* set interrupt when filled */
#define AHDLC_BD_RX_FIRST_FRAME_BIT   0x0800	/* First in frame */
#define AHDLC_BD_RX_LAST_FRAME_BIT	0x0400	/* last in frame */
#define AHDLC_BD_RX_CON_MODE_BIT		0x0200	/* Continuous Mode bit */
#define AHDLC_BD_RX_BREAK_BIT        		0x0080	/* break character bit */
#define AHDLC_BD_RX_FRAME_CLOSE_BIT	0x0040	/* begin of frame*/
#define AHDLC_BD_RX_AB_BIT				0x0008	/* Rx abort sequse */
#define AHDLC_BD_RX_CR_BIT				0x0004	/* Rx CRC error */
#define AHDLC_BD_RX_OV_BIT				0x0002	/* Overrun occurred */
#define AHDLC_BD_RX_CD_BIT				0x0001	/* Carrier detect lost */

/* Transmit BD status bits 16-bit value */

#define AHDLC_BD_TX_READY_BIT			0x8000	/* Transmit ready/busy bit */
#define AHDLC_BD_TX_WRAP_BIT			0x2000	/* last BD in chain */
#define AHDLC_BD_TX_INTERRUPT_BIT		0x1000	/* set interrupt when emptied */
#define AHDLC_BD_TX_LAST_FRAME_BIT	0x0800	/* last in frame */
#define AHDLC_BD_TX_CON_MODE_BIT		0x0200	/* Continuous Mode bit */
#define AHDLC_BD_TX_CT_BIT				0x0001	/* CTS lost */

#define AHDLC_BD_STATUS_OFFSET	0x00	/* two bytes */
#define AHDLC_BD_DATA_LENGTH_OFFSET	0x02	/* two bytes */
#define AHDLC_BD_BUF_POINTER_OFFSET	0x04	/* four bytes */



/* add AHDLC */
/*SICR*/
#define SCC_AHDLC_CLCMODE_8            	 0x00014000
#define SCC_AHDLC_CLCMODE_16          	 0x00028000
#define SCC_AHDLC_CLCMODE_32          	 0x0003c000
/*big edian    */
#define bit32(x)                                    ( 1<<(31-x) )  
#define bit16(x)                                    ( 1<<(15-x) )  
#define bit8(x)                                      ( 1<<(7-x) )  

#define BD_RX_FIRSTFRAME_BIT	0x0400	/* FIRST FRAME BIT */
#define BD_RX_LASTFRAME_BIT	0x0800	/* FIRST FRAME BIT */

/*    fpga cs  地址0xfca00064--> Bit0 */
/* Tx_ rx cs  Config Reg */
#define 	AHDLC_TX_CS()         ( *(CAST(VINT8 *)(0xfca00064) )   =  0xff) 
#define   AHDLC_RX_CS()         ( *(CAST(VINT8 *)(0xfca00064) )   =  0) 

STATUS ahdlcDrv  (    );
STATUS ahdlcDevCreate (    char *devName	 );
void timer3initial (void);
int	ahdlcAttach(void);

#ifdef __cplusplus
}
#endif

#endif	/* __INCmbxLptDrvh */