sccahdlcdrv.c

支持VXWORKES操作系统下MPC860系列处理器地异步HDLC驱动

/* SccAhdlctDrv.c - Asynchronous  HDLC device driver for mpc852 */
#include "copyright_wrs.h"


/*
DESCRIPTION

This is the driver for the Asynchronous  HDLC device driver on the mpc852 .

This driver currently supports only 1 chnnal.

*/
#include "assert.h"
#include "vxWorks.h"
#include "intLib.h"
#include "errno.h"
#include "sioLib.h"
#include "iv.h"
#include "drv\intrCtl\ppc860Intr.h"
#include "arch/ppc/vxPpcLib.h"
#include "ep8xx.h"
#include "taskLib.h"
#include "blkIo.h"
#include "ioLib.h"
#include "iosLib.h"
#include "memLib.h"
#include "stdlib.h"
#include "errnoLib.h"
#include "stdio.h"
#include "string.h"
#include "intLib.h"
#include "wdLib.h"
#include "sysLib.h"
#include "drv/multi/ppc860Siu.h"
#include "drv/multi/ppc860Cpm.h"
#include "drv/sio/ppc860Sio.h"
#include "drv/timer/timerDev.h"
#include "sys/fcntlcom.h"
#include "semLib.h"
#include "SccAhdlcDrv.h"
#include "../bsp/regDef.h"

#include "ep8xx.h"

#define INCLUDE_AHDLC

#ifdef INCLUDE_AHDLC


/*#define   AHDLC_USE_TIME3*/

#ifdef      M_DEBUG
	#define   debug(x)               printf x
#else
	#define debug(x)
#endif	



#ifdef AHDLC_CRC16

#define PPPINITFCS16    0xffff  /* Initial FCS value */
#define PPPGOODFCS16    0xf0b8  /* Good final FCS value */

const  UINT16 fcstab[256] = {
	0x0000, 0x1189, 0x2312, 0x329b, 0x4624, 0x57ad, 0x6536, 0x74bf,
	0x8c48, 0x9dc1, 0xaf5a, 0xbed3, 0xca6c, 0xdbe5, 0xe97e, 0xf8f7,
	0x1081, 0x0108, 0x3393, 0x221a, 0x56a5, 0x472c, 0x75b7, 0x643e,
	0x9cc9, 0x8d40, 0xbfdb, 0xae52, 0xdaed, 0xcb64, 0xf9ff, 0xe876,
	0x2102, 0x308b, 0x0210, 0x1399, 0x6726, 0x76af, 0x4434, 0x55bd,
	0xad4a, 0xbcc3, 0x8e58, 0x9fd1, 0xeb6e, 0xfae7, 0xc87c, 0xd9f5,
	0x3183, 0x200a, 0x1291, 0x0318, 0x77a7, 0x662e, 0x54b5, 0x453c,
	0xbdcb, 0xac42, 0x9ed9, 0x8f50, 0xfbef, 0xea66, 0xd8fd, 0xc974,
	0x4204, 0x538d, 0x6116, 0x709f, 0x0420, 0x15a9, 0x2732, 0x36bb,
	0xce4c, 0xdfc5, 0xed5e, 0xfcd7, 0x8868, 0x99e1, 0xab7a, 0xbaf3,
	0x5285, 0x430c, 0x7197, 0x601e, 0x14a1, 0x0528, 0x37b3, 0x263a,
	0xdecd, 0xcf44, 0xfddf, 0xec56, 0x98e9, 0x8960, 0xbbfb, 0xaa72,
	0x6306, 0x728f, 0x4014, 0x519d, 0x2522, 0x34ab, 0x0630, 0x17b9,
	0xef4e, 0xfec7, 0xcc5c, 0xddd5, 0xa96a, 0xb8e3, 0x8a78, 0x9bf1,
	0x7387, 0x620e, 0x5095, 0x411c, 0x35a3, 0x242a, 0x16b1, 0x0738,
	0xffcf, 0xee46, 0xdcdd, 0xcd54, 0xb9eb, 0xa862, 0x9af9, 0x8b70,
	0x8408, 0x9581, 0xa71a, 0xb693, 0xc22c, 0xd3a5, 0xe13e, 0xf0b7,
	0x0840, 0x19c9, 0x2b52, 0x3adb, 0x4e64, 0x5fed, 0x6d76, 0x7cff,
	0x9489, 0x8500, 0xb79b, 0xa612, 0xd2ad, 0xc324, 0xf1bf, 0xe036,
	0x18c1, 0x0948, 0x3bd3, 0x2a5a, 0x5ee5, 0x4f6c, 0x7df7, 0x6c7e,
	0xa50a, 0xb483, 0x8618, 0x9791, 0xe32e, 0xf2a7, 0xc03c, 0xd1b5,
	0x2942, 0x38cb, 0x0a50, 0x1bd9, 0x6f66, 0x7eef, 0x4c74, 0x5dfd,
	0xb58b, 0xa402, 0x9699, 0x8710, 0xf3af, 0xe226, 0xd0bd, 0xc134,
	0x39c3, 0x284a, 0x1ad1, 0x0b58, 0x7fe7, 0x6e6e, 0x5cf5, 0x4d7c,
	0xc60c, 0xd785, 0xe51e, 0xf497, 0x8028, 0x91a1, 0xa33a, 0xb2b3,
	0x4a44, 0x5bcd, 0x6956, 0x78df, 0x0c60, 0x1de9, 0x2f72, 0x3efb,
	0xd68d, 0xc704, 0xf59f, 0xe416, 0x90a9, 0x8120, 0xb3bb, 0xa232,
	0x5ac5, 0x4b4c, 0x79d7, 0x685e, 0x1ce1, 0x0d68, 0x3ff3, 0x2e7a,
	0xe70e, 0xf687, 0xc41c, 0xd595, 0xa12a, 0xb0a3, 0x8238, 0x93b1,
	0x6b46, 0x7acf, 0x4854, 0x59dd, 0x2d62, 0x3ceb, 0x0e70, 0x1ff9,
	0xf78f, 0xe606, 0xd49d, 0xc514, 0xb1ab, 0xa022, 0x92b9, 0x8330,
	0x7bc7, 0x6a4e, 0x58d5, 0x495c, 0x3de3, 0x2c6a, 0x1ef1, 0x0f78
};

/* Calculate a new fcs given the current fcs and the new data.*/
UINT16  pppfcs16( UINT16  ufcs,  unsigned char *pcp,  int ilen)
{	
	register UINT16  fcs = ufcs;
	register unsigned char *cp = pcp;
	register int len = ilen;
	
	while (len--)
		fcs = (fcs >> 8) ^ fcstab[(fcs ^ *cp++) & 0xff];

	return (fcs);
}
/*
* How to use the fcs
*/

STATUS  checkfcs16(const unsigned char *pcp,  int ilen)
{
	UINT16  trialfcs;
	STATUS   status = ERROR ;
	register unsigned char *cp;
	register int len = ilen ;
	cp = pcp;
	/* check on input */
	trialfcs = pppfcs16( PPPINITFCS16, cp, len );
	if ( trialfcs == PPPGOODFCS16 )
	{
		
		status = OK ;
	}
    return status ;
}



#endif

#define USE_DMA 


SCC_AHDLC_DEV	sccDev[SCC_NUM];
static int 	ahdlcDrvNum = 0 ;	/* driver number assigned to this driver */

/*int count,rxbcont,rxfcont;*/

BUFM_BUF usrbuf[SCC_AHDLC_RECV_BUF_NUM];
#ifndef USE_DMA
UINT8  txpbbuf[SCC_NUM_TBD][SCC_AHDL_FRAME_SIZE];
UINT8  rxpbbuf[SCC_NUM_RBD][SCC_AHDL_FRAME_SIZE];
#endif

static	int	ahdlcOpen		(DEV_HDR*pDev, char *name, int mode);
static	int	ahdlcRead		(int deviceid, char *pBuf, int buflen);
static	int	ahdlcWrite		(int deviceid, char *pBuf, int buflen);
static	int	ahdlcIoctl	(int deviceid, int cmd, int arg);
static	int	ahdlcClose(int deviceid);




#ifdef AHDLC_USE_TIME3

#define	CPM_MEM_BASE		0xFA200000

void timer3IntISR (void);
void timer3Enable (void);
void timer3Disable (void);


/*******************************************************************************
*
* timer3inition -initial  clock interrupts
*
* This routine enables auxiliary clock interrupts.
*
* RETURNS: N/A
*
* SEE ALSO: timer3Connect(), timer3Disable(), timer3RateSet()
*/

void timer3initial (void)
    {
    EPCFG  *cfg = getEpCfg();
    UINT32    tempDiv ;
    int timer3TicksPerSecond  =1000;
	
    tempDiv = cfg->sysCpuFreq / (timer3TicksPerSecond << 4);

  
        /* start, reset, but disable timer2 */
       
        *TGCR(CPM_MEM_BASE) &= ~(TGCR_RST3 |  TGCR_CAS2);
	/* *TGCR(CPM_MEM_BASE) |=  TGCR_STP3 ;*/
        *TCN3(CPM_MEM_BASE) = 0x0;

	if (tempDiv <= USHRT_MAX)
	    {
            *TRR3(CPM_MEM_BASE) = (UINT16) tempDiv;
            *TMR3(CPM_MEM_BASE) = (TMR_ICLK_IN_GEN | TMR_ORI |
                                   TMR_FRR | (TMR_PS_MSK & 0x0f00));
	    }
	else
	    {
            *TRR3(CPM_MEM_BASE) = (UINT16) (tempDiv / 16);
            *TMR3(CPM_MEM_BASE) = (TMR_ICLK_IN_GEN_DIV16 | TMR_ORI |
                                   TMR_FRR | (TMR_PS_MSK & 0x0f00));
	    }
	   *TER3(CPM_MEM_BASE) = 0xffff;		/* clear event */
	
            (void) intConnect (IV_TIMER3, (VOIDFUNCPTR) timer3IntISR, 0);

	
        *CIMR(CPM_MEM_BASE) |= CISR_TIMER3;	 /* unmask interupt */ 
	
    }



/*******************************************************************************
*
* timer3Enable - turn on auxiliary clock interrupts
*
* This routine enables auxiliary clock interrupts.
*
* RETURNS: N/A
*
* SEE ALSO: timer3Connect(), timer3Disable(), timer3RateSet()
*/

void timer3Enable (void)
    {
   
        *TER3(CPM_MEM_BASE) = 0xffff;		/* clear event */
	  *TCN3(CPM_MEM_BASE) = 0x0;	
        *CIMR(CPM_MEM_BASE) |= CISR_TIMER3;	 /* unmask interupt */
	 *TGCR(CPM_MEM_BASE) &= ~TGCR_STP3 ;	/* normal operation*/
        *TGCR(CPM_MEM_BASE) |= TGCR_RST3;	/* enable timer3 */

	
    }
/*******************************************************************************
*
* timer3Disable - turn off auxiliary clock interrupts
*
* This routine disables auxiliary clock interrupts.
*
* RETURNS: N/A
*
* SEE ALSO: timer3Enable()
*/

void timer3Disable (void)
    {
    
	/* *CIMR(CPM_MEM_BASE) &= ~CISR_TIMER3; */	/* disable interrupt */
	*TGCR(CPM_MEM_BASE) |= TGCR_STP3;	/* stop timer */
	
    }

/*******************************************************************************
*
* timer3Int - auxiliary clock interrupt handler
*
* This routine handles the auxiliary clock interrupt.  It calls a user routine
* if one was specified by the routine timer3Connect().
*/

 void timer3IntISR (void)
    {
   /* logMsg(" T3 hter3 = %x , CIMR= %x   tgcr =%x \n" ,   *TER3(CPM_MEM_BASE) ,*CIMR(CPM_MEM_BASE) , *TGCR(CPM_MEM_BASE)   );*/
    *TER3(CPM_MEM_BASE) |= TER_REF;     /* clear event register */
    *CISR(CPM_MEM_BASE) = CISR_TIMER3;  /* clear in-service bit */
   	
	AHDLC_RX_CS();
	
   	timer3Disable();

	semGive ( sccDev[0].writeSem  );	
	sccDev[0].ready_to_write =TRUE;
	selWakeupAll(  &sccDev[0].selWakeupkist , SELWRITE);
     /* logMsg(" T3 \n");*/
    }

#endif

void init_ports()
{
	int immrval;
	

      EPCFG  *cfg = getEpCfg();
      debug(("sys baudrate 0x %x \n ", cfg->sysBrgClkFreq));
	
	immrval = vxImmrGet();
	
	*PAPAR(immrval) |= 0x00c0;
	
	*SICR(immrval) &= 0x00ffffff;
	/*  select NMSI mode. SS4  connect  BRG$*/
	*SICR(immrval) |= 0x1b000000;
	
        AHDLC_RX_CS();


}

/*
*			init_tranBD(sccno);
*			initialize transmite BD
 */
 
void init_tranBD(SCC_AHDLC_DEV  * pSccDev)
{	
	int i;
	unsigned int 	bufaddress = (unsigned int)(pSccDev->ptran_buf_base);

	for(i = 0; i < SCC_NUM_TBD; i++)
	{
		pSccDev->ptran_BD[i].statusMode = 0x0;
		pSccDev->ptran_BD[i].dataLength = 0x0;
		pSccDev->ptran_BD[i].dataPointer =  (unsigned char *)bufaddress;
		bufaddress += SCC_AHDL_FRAME_SIZE;
	}
	

	pSccDev->ptran_BD[SCC_NUM_TBD-1].statusMode |= BD_TX_WRAP_BIT;
}

/*
 *	init_recvBD(sccno)
 *	initialize the recv BDs
 */
 
void init_recvBD(SCC_AHDLC_DEV  * pSccDev)
{	
	
	int i;
	unsigned int bufaddress = (unsigned int)(pSccDev->precv_buf_base );
	
	for(i = 0; i < SCC_NUM_RBD; i++)
	{
		pSccDev->precv_BD[i].statusMode = BD_RX_EMPTY_BIT | BD_RX_INTERRUPT_BIT ;
		pSccDev->precv_BD[i].dataLength = 0x0;
		pSccDev->precv_BD[i].dataPointer = (unsigned char *)bufaddress ;
		bufaddress += SCC_AHDL_FRAME_SIZE;
	}


	
	pSccDev->precv_BD[SCC_NUM_RBD-1].statusMode |= BD_RX_WRAP_BIT;
	
}

/*********************************************************** 
*  sccCpcrCommand - SCC CPCR命令处理子程序 
* 
*  RETURNS:
*			成功：_eMccSuccess
*			失败：错误ID 
*/ 
int sccCpcrCommand( UINT16 command, SCC_AHDLC_DEV *pSccDev )
{
    int		    immrVal;
    UINT16 		cpcrVal = 0;		 /* a convenience */
    UINT32	    ix = 0;	                 /* a counter */

	immrVal = pSccDev->immrVal;
	
    /* wait until the CP is clear，说明CPCR可用 */
    do {
		cpcrVal = *CPCR(immrVal);

		if ( ix++ >= SCC_CPCR_DELAY )
			break;
    } while ( cpcrVal & CPM_CR_FLG );

    if ( ix >= SCC_CPCR_DELAY ) 
    {
		return _eSCCCpcrCmdExecErr;
    }

    /* issue the command to the CP */
	#if 0
	if(0 == sccno)
	{
		cpcrVal = command | CPCR_CHNUM_SCC3 | CPM_CR_FLG;
	}
	else
	{
	#endif
		cpcrVal = command | CPCR_CHNUM_SCC4 | CPM_CR_FLG;
	#if 0
	}
	#endif

	*CPCR(immrVal) = cpcrVal;


    /* wait until the CP is clear，说明CPCR可用 */
    ix = 0;
    do {
		cpcrVal = *CPCR(immrVal);
		
		if ( ix++ >= SCC_CPCR_DELAY )
			break;
    } while ( cpcrVal & CPM_CR_FLG );
	
    if ( ix >= SCC_CPCR_DELAY ) 
    {
		return _eSCCCpcrCmdExecErr;
    }
    return _eSCCSuccess;
}

/*
 *	sccParaInit(sccno)
 *	initialize scc parameters
 */