int.c

ADC图形图像例子

/************************************************************************
 * File: int.c
 *
 * Copyright: Peak Microtech Corporation
 *
 ***********************************************************************/
 
 


#include "net_cfg.h"
#include "GLOBAL.h"

long _vgSDK_Cache_Flag;

extern void start();

void NMI(){}
void SWI7(){}
void AUTO_INT(){}

void TIMER0(){}
void TIMER1()
{
	TIMER1_Event();
	_ISR_END(_INT_NO_TIMER1);
}

void V_ENGINE(){}
void SIO(){}
void EXT_IRQ0(){}
void EXT_IRQ1(){}
void DMA0(){}
void DMA1(){}
void TIMER2(){}
void TIMER3(){}
void EXT_IRQ2(){}
void EXT_IRQ3(){}
void UART0_ER(){}
void UART0_RX(){}
void UART0_TX(){}
void UART1_ER(){}
void UART1_RX(){}
void UART1_TX(){}
void VSP(){}
void PWM(){}

/* Interrupt vector table */
volatile fp HardwareVector[]__attribute__((section(".vects"))) =
{
	/* Reset Vector */
	start,  /* V00 : Reset Vector            */
	NMI,  /* V01 : NMI Vector              */
	AUTO_INT,  /* V02 : Interrupt Auto Vector   */
	NOTUSEDISR,  /* V03 : Double Falule Exception */
	NOTUSEDISR,  /* V04 : Bus Error exception     */
	NOTUSEDISR,  /* V05 : Reserved                */
	NOTUSEDISR,  /* V06 : Reserved                */
	NOTUSEDISR,  /* V07 : Reserved                */
	NOTUSEDISR,  /* V08 : Co-processor Exception  */
	NOTUSEDISR,  /* V09 : Co-processor Exception  */
	NOTUSEDISR,  /* V0A : Co-processor Exception  */
	NOTUSEDISR,  /* V0B : Co-processor Exception  */
	NOTUSEDISR,  /* V0C : OSI Reset Vector        */
	NOTUSEDISR,  /* V0D : OSI break exception     */
	NOTUSEDISR,  /* V0E : Reserved                */
	NOTUSEDISR,  /* V0F : Reserved                */
	NOTUSEDISR,  /* V10 : SWI 00 Vector           */
	NOTUSEDISR,  /* V11 : SWI 01 Vector           */
	NOTUSEDISR,  /* V12 : SWI 02 Vector           */
	NOTUSEDISR,  /* V13 : SWI 03 Vector           */
	NOTUSEDISR,  /* V14 : SWI 04 Vector           */
	NOTUSEDISR,  /* V15 : SWI 05 Vector           */
	NOTUSEDISR,  /* V16 : SWI 06 Vector           */
	SWI7,  /* V17 : SWI 07 Vector           */
	NOTUSEDISR,  /* V18 : SWI 08 Vector           */
	NOTUSEDISR,  /* V19 : SWI 09 Vector           */
	NOTUSEDISR,  /* V1A : SWI 0A Vector           */
	NOTUSEDISR,  /* V1B : SWI 0B Vector           */
	NOTUSEDISR,  /* V1C : SWI 0C Vector           */
	NOTUSEDISR,  /* V1D : SWI 0D Vector           */
	NOTUSEDISR,  /* V1E : SWI 0E Vector           */
	NOTUSEDISR,  /* V1F : SWI 0F Vector           */

	TIMER0,  /* V20 : User 00 Vector          */
	TIMER1,  /* V21 : User 01 Vector          */
	V_ENGINE,  /* V22 : User 02 Vector          */
	SIO,  /* V23 : User 03 Vector          */
	NOTUSEDISR,  /* V24 : User 04 Vector          */
	EXT_IRQ0,  /* V25 : User 05 Vector          */
	EXT_IRQ1,  /* V26 : User 06 Vector          */
	DMA0,  /* V27 : User 07 Vector          */
	DMA1,  /* V28 : User 08 Vector          */
	TIMER2,  /* V29 : User 09 Vector          */
	TIMER3,  /* V2A : User 0A Vector          */
	EXT_IRQ2,  /* V2B : User 0B Vector          */
	EXT_IRQ3,  /* V2C : User 0C Vector          */
	UART0_ER,  /* V2D : User 0D Vector          */
	UART0_RX,  /* V2E : User 0E Vector          */
	UART0_TX,  /* V2F : User 0F Vector          */

	UART1_ER,  /* V30 : User 0F Vector          */
	UART1_RX,  /* V31 : User 10 Vector          */
	UART1_TX,  /* V32 : User 11 Vector          */
	NOTUSEDISR,  /* V33 : User 12 Vector          */
	NOTUSEDISR,  /* V34 : User 13 Vector          */
	NOTUSEDISR,  /* V35 : User 14 Vector          */
	NOTUSEDISR,  /* V36 : User 15 Vector          */
	NOTUSEDISR,  /* V37 : User 16 Vector          */
	VSP,  /* V38 : User 17 Vector          */
	NOTUSEDISR,  /* V39 : User 18 Vector          */
	PWM,  /* V3A : User 19 Vector          */
	NOTUSEDISR,  /* V3B : User 1A Vector          */
	NOTUSEDISR,  /* V3C : User 1B Vector          */
	NOTUSEDISR,  /* V3D : User 1C Vector          */
	NOTUSEDISR,  /* V3E : User 1D Vector          */
	NOTUSEDISR,  /* V3F : User 1E Vector          */

	NOTUSEDISR,  /* V40 : User 1F Vector          */
	NOTUSEDISR,  /* V41 : User 20 Vector          */
	NOTUSEDISR,  /* V42 : User 21 Vector          */
	NOTUSEDISR,  /* V43 : User 22 Vector          */
	NOTUSEDISR,  /* V44 : User 23 Vector          */
	NOTUSEDISR,  /* V45 : User 24 Vector          */
	NOTUSEDISR,  /* V46 : User 25 Vector          */
	NOTUSEDISR,  /* V47 : User 26 Vector          */
	NOTUSEDISR,  /* V48 : User 27 Vector          */
	NOTUSEDISR,  /* V49 : User 28 Vector          */
	NOTUSEDISR,  /* V4A : User 29 Vector          */
	NOTUSEDISR,  /* V4B : User 2A Vector          */
	NOTUSEDISR,  /* V4C : User 2B Vector          */
	NOTUSEDISR,  /* V4D : User 2C Vector          */
	NOTUSEDISR,  /* V4E : User 2D Vector          */
	NOTUSEDISR,  /* V4F : User 2E Vector          */
};

void InitInterrupt(void)
{
	_DISABLE_INT();

	// Disable all interrupt
	_REG_INT_EN = 0x0UL;
	// set baseaddress for vectored mode
	_REG_INT_VEC = _ISR_HIGH_3BIT;
	// set vectored mode interrupt.
	_SET_VECTORED_MODE_INT();

	_ENABLE_INT();
}


void _vgSDK_Cache_Reset()
{
	volatile U32 temp;
	volatile U32 *ptemp;
	volatile U32 i;
	if (_vgSDK_Cache_Flag == 0)
		return ;
	ptemp = (volatile U32*)0x02000000;
	for (i = 0; i < CACHE_SIZE; i++)
		temp =  *ptemp++;
}


void vgSetInterruptVector(int num, void(*event)())
{
	HardwareVector[num] = event;
	_vgSDK_Cache_Reset();
}


U32 vgGetSysFreq()
{
	U32 temp_reg;
	float system_freq;

	if ((*(volatile U8*)REG_CFGR) &0x40)
	{
		//system_freq = ((M+8)*fin)/((P+2)*(0x01<<S))->Internal Clock
		temp_reg = *(volatile U16*)REG_PLPGM; // PLL Control Register Read
		system_freq = (float)((((temp_reg >> 8) &0xff) + 8) *XIN) / ((float)((
	(temp_reg >> 2) &0x03f) + 2)*(float)(1 << (temp_reg &0x3)));

	}
	else
	// Internal PLL Clock
	{
		// External Clock
		system_freq = XIN;
	}

	return (U32)system_freq;
}


void(*_vgTimer1Event)() = vgNULL;


void _Timer1TickEvent(void)
{
	if (_vgTimer1Event)
		_vgTimer1Event();
	_ISR_END(_INT_NO_TIMER1);
}

void vgInitTimer1(void(*event)(), U32 vr0clock)
{
	U32 temp = vr0clock / (2 *1000000) - 1;

	_DISABLE_INT();

	_vgTimer1Event = event;
	vgSetInterruptVector(_INT_BASE_OFFSET + _INT_NO_TIMER1, _Timer1TickEvent);

	// Timer1 : count * usec, continuous loop, enable
	temp = (temp << _TIMER_PRESCALER_SHIFT) | _TIMER_OPERATION_CONTINUE;

	_REG_TIMER1_CON = (U16)temp; // usec clock
	_REG_TIMER1_CNT = 65535;

	// Timer1 INT Enable
	temp = _REG_INT_EN;
	temp |= _INT_TIMER1;
	_REG_INT_EN = temp;

	_ENABLE_INT();
}


void vgSetTimer1(U16 usec)
{
	U16 temp;

	// stop timer1
	temp = _REG_TIMER1_CON;
	temp &= ~(_TIMER_ENABLE);
	_REG_TIMER1_CON = temp;

	if (usec != 0)
		usec--;
	_REG_TIMER1_CNT = usec;

	// run timer1
	temp |= _TIMER_ENABLE;
	_REG_TIMER1_CON = temp;

}


void vgStopTimer1(void)
{
	U16 temp;

	_DISABLE_INT();

	// Stop Timer1
	temp = _REG_TIMER1_CON;
	temp &= ~(_TIMER_ENABLE);
	_REG_TIMER1_CON = temp;

	// Timer1 INT Disable
	temp = _REG_INT_EN;
	temp &= ~(_INT_TIMER1);
	_REG_INT_EN = temp;

	_ENABLE_INT();
}

//*============================================================/

// Initialize Net Interrput
void Net_Interrupt_Init(void)
{
	U32 Freq;
	// Disable Cache
	_vgSDK_Cache_Flag = 0;

	// Initialize Interrupt
	InitInterrupt();
	// Get System Frequency
	Freq = vgGetSysFreq();
	// Initialize Timer1
	vgInitTimer1(TIMER1, Freq);
	vgSetTimer1(20002); // 10MS
}