📄 register.h
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/************************************************************************
* File: register.h
*
* Copyright: Peak Microtech Corporation
*
***********************************************************************/
#ifndef _REGISTER_H
#define _REGISTER_H
/* System / Geral Registers */
#define REG_SYSID 0x01800000 // System ID Register
#define REG_CFGR 0x01800004 // Configuration Register
#define REG_SYSCON 0x01800008 // System Control Register
#define REG_WDCON 0x01800010 // Watch Dog Timer Control Register
#define REG_WDCNT 0x01800014 // watch Dog Timer Count Register
#define REG_PMCR1 0x01800018 // Pin Mux Control Register1
#define REG_PMCR2 0x0180001c // Pin Mux Control Register2
/* Memory Control Registers */
#define REG_MCON 0x01800400 // Local ROM & SDRAM Clock Control Register
#define REG_LDCON 0x01800408 // Local DRAM Control Register
/* DMA */
#define REG_DMAC0 0x01800800 // DMA0 Control Register
#define REG_DMASA0 0x01800804 // DMA0 Source Address Register
#define REG_DMADA0 0x01800808 // DMA0 Destination Address Register
#define REG_DMATC0 0x0180080c // DMA0 Transfer Count Register
#define REG_DMAC1 0x01800810 // DMA1 Control Register
#define REG_DMASA1 0x01800814 // DMA1 Source Address Register
#define REG_DMADA1 0x01800818 // DMA1 Destination Address Register
#define REG_DMATC1 0x0180081c // DMA1 Transfer Count Register
/* Interrupt Controller */
#define REG_INTMOD 0x01800c00 // Interrupt Mode Register
#define REG_INTVEC 0x01800c04 // Interrupt Vector Register
#define REG_INTEN 0x01800c08 // Interrupt Enable Register
#define REG_INTST 0x01800c0c // Interrupt Status Register
/* UART */
#define REG_UCON0 0x01801000 // UART Channel 0 Control Register
#define REG_USTAT0 0x01801004 // UART Channel 0 Status Register
#define REG_UTXB0 0x01801008 // UART Channel 0 Transmit Buffer Register
#define REG_URXB0 0x0180100c // UART Channel 0 Receive Buffer Register
#define REG_UBDR0 0x01801010 // UART Channel 0 Baud Rate Devisor Register
#define REG_UCON1 0x01801020 // UART Channel 1 Control Register
#define REG_USTAT1 0x01801024 // UART Channel 1 Status Register
#define REG_UTXB1 0x01801028 // UART Channel 1 Transmit Buffer Register
#define REG_URXB1 0x0180102c // UART Channel 1 Receive Buffer Register
#define REG_UBDR1 0x01801030 // UART Channel 1 Baud Rate Devisor Register
/* Timer */
#define REG_TMCON0 0x01801400 // Timer0 Control Register
#define REG_TMCNT0 0x01801404 // Timer0 Count Register
#define REG_TMCON1 0x01801408 // Timer1 Control Register
#define REG_TMCNT1 0x0180140c // Timer1 Count Register
#define REG_TMCON2 0x01801410 // Timer2 Control Register
#define REG_TMCNT2 0x01801414 // Timer2 Count Register
#define REG_TMCON3 0x01801418 // Timer3 Control Register
#define REG_TMCNT3 0x0180141c // Timer3 Count Register
/* Pulse Width Modulation */
#define REG_PMCON 0x01801800 // PWM Control Register
#define REG_PMDTY 0x01801804 // PWM Duty Register
#define REG_PMPRD 0x01801808 // PWM Period Register
#define REG_PULCNT 0x0180180c // Pulse Count Register
/* Synchronous Serial IO */
#define REG_SIOCON 0x01802800 // SIO Control Register
#define REG_SIODAT 0x01802804 // SIO Data Register
#define REG_SIOBDR 0x01802808 // SIO Baud Rate Prescaler Register
#define REG_SIOICNT 0x0180280c // SIO Interval Count Register
#define REG_SIOSTAT 0x01802810 // SIO Status Register
/* PIO */
#define REG_PIOMOD 0x01802000 // PIO Mode Register
#define REG_PIOLDAT 0x01802004 // PIO Latched Output Data Register
#define REG_PIOEDAT 0x01802008 // PIO External Data Register
/* Peripheral Device Chip Set */
#define REG_CS0CON 0x01802400 // PCS0 Control Register
#define REG_CS1CON 0x01802404 // PCS1 Control Register
#define REG_CS2CON 0x01802408 // PCS2 Control Register
#define REG_CS3CON 0x0180240c // PCS3 Control Register
#define REG_CS4CON 0x01802410 // PCS4 Control Register
#define REG_CS5CON 0x01802414 // PCS5 Control Register
#define REG_CS6CON 0x01802418 // PCS6 Control Register
#define REG_CS7CON 0x0180241c // PCS7 Control Register
/* CRT Controller */
#define REG_CRTMOD 0x01803400 // CRTC Status/Mode Register
#define REG_CRTTIM 0x01803404 // CRTC Timing Control Register
#define REG_HSWBP 0x01803408 // Horizontal Sync Width/Back Porch Register
#define REG_HDISP 0x0180340c // Horizontal Display Total Register
#define REG_HSFP 0x01803410 // Horizontal Sync Front Porch Register
#define REG_FWINB 0x01803414 // Field Window Bound Register
#define REG_VSBP 0x01803418 // Vertical Sync Back Porch Register
#define REG_VDISP 0x0180341c // Vertical Display Total Register
#define REG_HTOT 0x01803420 // Horizontal Total Register
#define REG_VTOT 0x01803424 // Vertical Total Register
#define REG_HLBP 0x01803428 // Horizontal Line Back Porch Register
#define REG_STAD0 0x0180342c // CRT Display Start Address 0 Register
#define REG_STAD1 0x01803430 // CRT Display Start Address 1 Register
#define REG_LIGHT0X 0x01803438 // Light Pen 0 X Register
#define REG_LIGHT0Y 0x0180343c // Light Pen 0 Y Register
#define REG_LIGHT1X 0x01803440 // Light Pen 1 X Register
#define REG_LIGHT1Y 0x01803444 // Light Pen 1 Y Register
#define REG_LIGHTC 0x01803448 // Light Pe Input Control Register
/* Frequency Synthesizer */
#define REG_DPCON 0x01804000 // PLL Control Register
#define REG_PLPGM 0x01804004 // PLL Program Register
/* Graphic Controller */
#define REG_CQFP 0x03000080 // Command Queue Front Pointer Register
#define REG_CQRP 0x03000082 // Command Queue Rear Pointer Register
#define REG_REC 0x0300008c // Rendering Engine Control Register
#define REG_DBR 0x0300008e // Display Bank Register
#define REG_RB1AS 0x03000090 // Rendering Bank1 Address Select Register
#define REG_FCC 0x030000a6 // Flip Command Count Register
#define REG_TFCTRL 0x03000100 // TMEM/FMEM Control Register
#define REG_FMEMTIM 0x03000106 // FMEM Timing Control Register
#define REG_TMEMTIM 0x03000108 // TMEM Timing Control Register
/* Sound Channel Parameter Register */
#define REG_CURADL 0x04800000 // CurSAddr 15-0
#define REG_CURADH 0x04800002 // CurSAddr 31-16
#define REG_ENVOLL 0x04800004 // Envelope Volume 15-0
#define REG_ENVOLH 0x04800006 // Envelope Volume 23-16
#define REG_ESTAGE 0x04800006 // Envelope State
#define REG_DSADDR 0x04800008 // DSaddr 15-0
#define REG_SNDMOD 0x0480000a // Modes
#define REG_LOPBNL 0x0480000c // Loop Begin 15-0
#define REG_LOPBNH 0x0480000e // Loop Begin 21-16
#define REG_LCHVOL 0x0480000e // Left Channel Volume
#define REG_LOPENDL 0x04800010 // Loop End 15-0
#define REG_LOPENDH 0x04800012 // Loop End 21-16
#define REG_RCHVOL 0x04800012 // Right Channel Volume
#define REG_ENVRAT0 0x04800014 // Envelope Rate0
#define REG_ENVRAT1 0x04800016 // Envelope Rate1
#define REG_ENVRAT2 0x04800018 // Envelope Rate2
#define REG_ENVRAT3 0x0480001a // Envelope Rate3
#define REG_ENVTAG0 0x0480001c // Envelope Target0
#define REG_ENVTAG1 0x0480001c // Envelope Target1
#define REG_ENVTAG2 0x0480001e // Envelope Target2
#define REG_ENVTAG3 0x0480001e // Envelope Target3
/* Sound Engine Controller */
#define REG_STATUSL 0x04800404 // Status(Low): Channel 15-0
#define REG_STATUSH 0x04800406 // Status(High): Channel 31-16
#define REG_NOTEL 0x04800408 // Note On(Low): Channel 15-0
#define REG_NOTEH 0x0480040a // Note On(High): Channel 31-16
//#define REG_CHNOTE 0x04800408 // Channel Number for Note
#define REG_REVMUL 0x04800410 // Reverberation Mul
#define REG_BSADDR 0x04800412 // Buffer Select Address
#define REG_BSIZE0 0x04800420 // BufferSize0
#define REG_BSIZE1 0x04800422 // BufferSize1
#define REG_BSIZE2 0x04800440 // BufferSize2
#define REG_BSIZE3 0x04800442 // BufferSize3
#define REG_INMASKL 0x04800480 // IntMask(Low):Channel 15-0
#define REG_INMASKH 0x04800482 // IntMask(High):Channel 31-16
#define REG_INPENDL 0x04800500 // IntPend(Low):Channel 15-0
#define REG_INPENDH 0x04800502 // IntPend(High):Channel 31-16
#define REG_SNDCHCT 0x04800600 // Channel Control Register
#define REG_SNDCTRL 0x04800602 // Sound Control Register
/*******************************************************************************
*
* Register Bit Define
*
*******************************************************************************/
/*
Rendering engine control register BIT Define
*/
#define REN_BACK_BUFF 0x00 // Rendering Buffer Back
#define REN_FRONT_BUFF 0x80 // Rendering Buffer Front
#define REN_RESET 0x08 // Rendering Rese
#define REN_RUN 0x04 // Rendering Run
#define REN_DIT_DIS 0x02 // Rendering Dither Disable
#define REN_DIT_4x4 0x01 // Rendering Dither 4x4
#define REN_DIT_2x2 0x00 // rendering Dither 2x2
/*
Rendering Bank1 address select register Bit Define
*/
#define BANK1_410 0x0000 // Bank address 0x4100000
#define BANK1_440 0x8000 // Bank address 0x4400000
/*
TMEM/FMEM Control register(TFCTRL)
*/
#define TFRESET 0x0000 // TMEM/FMEM Reset
#define TFACTIVE 0x8000 // TMEM/FMEM Active
#define TSDM16MBIT 0x0000 // Texture SDRAM 16MBit
#define TSDM64MBIT 0x0008 // Testure SDRAM 64MBit
#define FSDM16MBIT 0x0000 // Frame SDRAM 16MBit
#define FSDM64MBIT 0x0002 // Frame SDRAM 64MBit
/************************* CRT Controller ************************************/
/*
CRTC Status/Mode Register(CRTMOD)
*/
#define BLANK_SCR (0x01 << 9) // Screen Blank Enable
#define CRTC_WEN (0x01 << 8) // CRTC Register Write Protect
#define H625Line (0x01 << 7) // Horizontal Scan Line Number
#define CBF4430000 (0x01 << 6) // Color Burst Frequency
#define NEV_POF (0x01 << 3) // Enven Field(NTSC), Odd Field(PAL)
#define INT_BLOCK (0x01 << 2) // VSYNC Select at Remote Mode->Internal block(Csync To VH)
#define POEQ_SERR (0x01 << 1) // Vertical Sync Width Generation->Post-equalization and Serration
#define PREQ_SERR (0x01 << 0) // Vertical Sync Width Generation->Pre-equalization and Serration
/*
CRTC Timing Control Register(CRTTIM)
*/
#define VCLK2TH (0x01 << 7) // 寇何辑 涝仿登绰 Video Clock(VCLK)郴何利栏肺 2眉硅 倾侩
#define VCLK14138 (0x01 << 3) // VCLK Select(郴何俊辑 惯积 (14.318MHz))
/*
CRTC Display Start Address 0 Register(STAD0)
*/
#define VFLIPEN (0x01 << 0) // Vertical Flip Enable
/*
CRTC Display Start Address 1 Register(STAD1)
*/
#define ODDFRAME (0x01 << 1) // Current Display Frame For Double Buffering at Interlace Mode
#define NONINTLACE (0x01 << 0) // Non Interlae Mode
#endif /* _REGISTER_H */
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