pic_core.vhd

一个PIC单片机内核的VHDL实现

-- means output-enable (i.e. put the value on the 3-state bus when this 
-- signal is high).  Refer to the other source files for the meanings of the 
-- other signals.

-- input/output configuration of the I/O ports.
SIGNAL port_a_tri : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL port_b_tri : STD_LOGIC_VECTOR(7 DOWNTO 0);
SIGNAL port_c_tri : STD_LOGIC_VECTOR(7 DOWNTO 0);

SIGNAL port_a_oen : STD_LOGIC;
SIGNAL port_b_oen : STD_LOGIC;
SIGNAL port_c_oen : STD_LOGIC;
SIGNAL port_a_wen : STD_LOGIC; 
SIGNAL port_b_wen : STD_LOGIC; 
SIGNAL port_c_wen : STD_LOGIC;
SIGNAL tris_a_wen : STD_LOGIC;
SIGNAL tris_b_wen : STD_LOGIC;
SIGNAL tris_c_wen : STD_LOGIC;
SIGNAL w_wen : STD_LOGIC;
SIGNAL w_a_oen : STD_LOGIC;
SIGNAL w_b_oen : STD_LOGIC;
SIGNAL pc_wen : STD_LOGIC;
SIGNAL pc_oen : STD_LOGIC;
SIGNAL pc_push : STD_LOGIC;
SIGNAL pc_pop : STD_LOGIC;
SIGNAL pc_load : STD_LOGIC;
SIGNAL fsr_wen : STD_LOGIC;
SIGNAL fsr_oen : STD_LOGIC;
SIGNAL rtcc_wen : STD_LOGIC;
SIGNAL rtcc_oen : STD_LOGIC;
SIGNAL file_wen : STD_LOGIC;
SIGNAL file_oen : STD_LOGIC;
SIGNAL inst_skip : STD_LOGIC;
SIGNAL imm_oen : STD_LOGIC;
SIGNAL status_oen : STD_LOGIC;
SIGNAL status_wen : STD_LOGIC;
SIGNAL carry_wen : STD_LOGIC;
SIGNAL zero_wen : STD_LOGIC;
SIGNAL const_oen : STD_LOGIC;
SIGNAL const_01 : STD_LOGIC;

BEGIN 

    rom : pic_rom PORT MAP
       (
         addr => pic_rom_addr,
         data => pic_rom_data
       );

    port_a_reg : reg_io PORT MAP
         (
           clock     => clock,
           out_en    => port_a_oen,
           write_en  => port_a_wen,
           data_in   => bus_out,
           data_out  => bus_a,
           inout_sel => port_a_tri,
           dataport  => port_a
         );

    port_b_reg : reg_io PORT MAP
         (
           clock     => clock,
           out_en    => port_b_oen,
           write_en  => port_b_wen,
           data_in   => bus_out,
           data_out  => bus_a,
           inout_sel => port_b_tri,
           dataport  => port_b
         );

    port_c_reg : reg_io PORT MAP
         (
           clock     => clock,
           out_en    => port_c_oen,
           write_en  => port_c_wen,
           data_in   => bus_out,
           data_out  => bus_a,
           inout_sel => port_c_tri,
           dataport  => port_c
         );

    working_register : reg_w PORT MAP
         (
           clock      => clock,
           out_a_en   => w_a_oen,
           out_b_en   => w_b_oen,
           write_en   => w_wen,
           data_in    => bus_out,
           data_a_out => bus_a,
           data_b_out => bus_b
         );

    io_conf_port_a : reg_8rst PORT MAP
         (
           clock     =>  clock,
           reset     =>  reset,
           write_en  =>  tris_a_wen,
           data_in   =>  bus_out,
           data_out  =>  port_a_tri
         );

    io_conf_port_b : reg_8rst PORT MAP
         (
           clock     =>  clock,
           reset     =>  reset,
           write_en  =>  tris_b_wen,
           data_in   =>  bus_out,
           data_out  =>  port_b_tri
         );
    
    io_conf_port_c : reg_8rst PORT MAP
         (
           clock     =>  clock,
           reset     =>  reset,
           write_en  =>  tris_c_wen,
           data_in   =>  bus_out,
           data_out  =>  port_c_tri
         );
    
    instruction_register : reg_inst PORT MAP
         (
           clock     =>  clock,
           reset     =>  reset,
           skip      =>  inst_skip,
           out_en    =>  imm_oen,
           inst_in   =>  pic_rom_data,
           inst_out  =>  inst,
           imm_out   =>  bus_b
         );
    
    fsr_register : reg_fsr PORT MAP
         (
           clock     =>  clock,
           out_en    =>  fsr_oen,
           write_en  =>  fsr_wen,
           data_in   =>  bus_out,
           data_out  =>  bus_a,
           fsr_out   =>  fsr
         );

    file_address_mux : fadr_mux PORT MAP
         (
           inst_5     => inst(4 DOWNTO 0),
           fsr        => fsr,
           file_addr  => file_addr
         );
    
    register_file : reg_file PORT MAP
         (
           clock    =>  clock,
           write_en =>  file_wen,
           out_en   =>  file_oen,
           address  =>  file_addr,
           data_in  =>  bus_out,
           data_out =>  bus_a
         );

    program_counter : reg_pc PORT MAP
         (
           clock     =>  clock,
           reset     =>  reset,
           out_en    =>  pc_oen,
           write_en  =>  pc_wen,
           data_in   =>  bus_out,
           data_out  =>  bus_a,
           addr_in   =>  inst(8 DOWNTO 0),
           addr_out  =>  pic_rom_addr,
           push      =>  pc_push,
           pop       =>  pc_pop,
           load      =>  pc_load
         );

    status_register : reg_s PORT MAP
         (
           clock     =>  clock,
           reset     =>  reset,
           out_en    =>  status_oen,
           write_en  =>  status_wen,
           data_in   =>  bus_out,
           data_out  =>  bus_a,
           carry_out =>  carry_old,
           carry_in  =>  carry_new,
           zero_in   =>  zero,
           carry_wr  =>  carry_wen,
           zero_wr   =>  zero_wen
         );

    constants_generator : reg_cons PORT MAP
         (
           out_en    => const_oen,
           const_01  => const_01,
           data_out  => bus_b
         );

    rtcc : reg_8t PORT MAP
         (
           clock     =>  clock,
           out_en    =>  rtcc_oen,
           write_en  =>  rtcc_wen,
           data_in   =>  bus_out,
           data_out  =>  bus_a
         );
    
    alu : pic_alu PORT MAP
       (
           operation  =>  alu_op,
           a          =>  bus_a,
           b          =>  bus_b,
           q          =>  bus_out,
           carry_in   =>  carry_old,
           carry_out  =>  carry_new,
           zero       =>  zero
       );

    controller : pic_ctrl PORT MAP
       (
         inst       =>  inst,
         file_addr  =>  file_addr,
         zero       =>  zero,
         alu_op     =>  alu_op,
         tris_a_wen =>  tris_a_wen,
         tris_b_wen =>  tris_b_wen,
         tris_c_wen =>  tris_c_wen,
         port_a_wen =>  port_a_wen,
         port_b_wen =>  port_b_wen,
         port_c_wen =>  port_c_wen,
         w_wen      =>  w_wen,
         w_a_oen    =>  w_a_oen,
         w_b_oen    =>  w_b_oen,
         pc_wen     =>  pc_wen,
         pc_oen     =>  pc_oen,
         pc_push    =>  pc_push,
         pc_pop     =>  pc_pop,
         pc_load    =>  pc_load,
         fsr_wen    =>  fsr_wen,
         fsr_oen    =>  fsr_oen,
         rtcc_wen   =>  rtcc_wen,
         rtcc_oen   =>  rtcc_oen,
         file_wen   =>  file_wen,
         file_oen   =>  file_oen,
         inst_skip  =>  inst_skip,
         imm_oen    =>  imm_oen,
         status_oen =>  status_oen,
         status_wen =>  status_wen,
         carry_wen  =>  carry_wen,
         zero_wen   =>  zero_wen,
         port_a_oen =>  port_a_oen,
         port_b_oen =>  port_b_oen,
         port_c_oen =>  port_c_oen,
         const_oen  =>  const_oen,
         const_01   =>  const_01
       );
    
END structural;