📄 multi8.rpt
字号:
_EQ012 = a7 & _LC1_A6;
-- Node name is '|reg16:U5|:43' = '|reg16:U5|r16s0'
-- Equation name is '_LC8_B1', type is buried
_LC8_B1 = DFFE( _LC7_B1, _LC1_A5, GLOBAL(!start), VCC, VCC);
-- Node name is '|reg16:U5|:42' = '|reg16:U5|r16s1'
-- Equation name is '_LC7_B1', type is buried
_LC7_B1 = DFFE( _LC5_B1, _LC1_A5, GLOBAL(!start), VCC, VCC);
-- Node name is '|reg16:U5|:41' = '|reg16:U5|r16s2'
-- Equation name is '_LC5_B1', type is buried
_LC5_B1 = DFFE( _LC1_B1, _LC1_A5, GLOBAL(!start), VCC, VCC);
-- Node name is '|reg16:U5|:40' = '|reg16:U5|r16s3'
-- Equation name is '_LC1_B1', type is buried
_LC1_B1 = DFFE( _LC2_B1, _LC1_A5, GLOBAL(!start), VCC, VCC);
-- Node name is '|reg16:U5|:39' = '|reg16:U5|r16s4'
-- Equation name is '_LC2_B1', type is buried
_LC2_B1 = DFFE( _LC3_B1, _LC1_A5, GLOBAL(!start), VCC, VCC);
-- Node name is '|reg16:U5|:38' = '|reg16:U5|r16s5'
-- Equation name is '_LC3_B1', type is buried
_LC3_B1 = DFFE( _LC8_B3, _LC1_A5, GLOBAL(!start), VCC, VCC);
-- Node name is '|reg16:U5|:37' = '|reg16:U5|r16s6'
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = DFFE( _LC2_B3, _LC1_A5, GLOBAL(!start), VCC, VCC);
-- Node name is '|reg16:U5|:36' = '|reg16:U5|r16s7'
-- Equation name is '_LC2_B3', type is buried
_LC2_B3 = DFFE( _EQ013, _LC1_A5, GLOBAL(!start), VCC, VCC);
_EQ013 = a0 & _LC1_A6 & !_LC3_B3
# !a0 & _LC3_B3
# !_LC1_A6 & _LC3_B3;
-- Node name is '|reg16:U5|:35' = '|reg16:U5|r16s8'
-- Equation name is '_LC3_B3', type is buried
_LC3_B3 = DFFE( _EQ014, _LC1_A5, GLOBAL(!start), VCC, VCC);
_EQ014 = a1 & _LC1_A6 & _LC4_B3 & _LC5_B3
# !_LC1_A6 & _LC4_B3 & !_LC5_B3
# !a1 & _LC4_B3 & !_LC5_B3
# !_LC1_A6 & !_LC4_B3 & _LC5_B3
# !a1 & !_LC4_B3 & _LC5_B3
# a1 & _LC1_A6 & !_LC4_B3 & !_LC5_B3;
-- Node name is '|reg16:U5|:34' = '|reg16:U5|r16s9'
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = DFFE( _EQ015, _LC1_A5, GLOBAL(!start), VCC, VCC);
_EQ015 = a2 & _LC1_A6 & _LC5_B2 & _LC6_B3
# !a2 & !_LC5_B2 & _LC6_B3
# !_LC1_A6 & !_LC5_B2 & _LC6_B3
# !a2 & _LC5_B2 & !_LC6_B3
# !_LC1_A6 & _LC5_B2 & !_LC6_B3
# a2 & _LC1_A6 & !_LC5_B2 & !_LC6_B3;
-- Node name is '|reg16:U5|:33' = '|reg16:U5|r16s10'
-- Equation name is '_LC5_B2', type is buried
_LC5_B2 = DFFE( _EQ016, _LC1_A5, GLOBAL(!start), VCC, VCC);
_EQ016 = a3 & _LC1_A6 & _LC1_B3 & _LC3_B2
# !a3 & _LC1_B3 & !_LC3_B2
# !_LC1_A6 & _LC1_B3 & !_LC3_B2
# !a3 & !_LC1_B3 & _LC3_B2
# !_LC1_A6 & !_LC1_B3 & _LC3_B2
# a3 & _LC1_A6 & !_LC1_B3 & !_LC3_B2;
-- Node name is '|reg16:U5|:32' = '|reg16:U5|r16s11'
-- Equation name is '_LC3_B2', type is buried
_LC3_B2 = DFFE( _EQ017, _LC1_A5, GLOBAL(!start), VCC, VCC);
_EQ017 = a4 & _LC1_A6 & _LC2_B2 & _LC8_B2
# !a4 & !_LC2_B2 & _LC8_B2
# !_LC1_A6 & !_LC2_B2 & _LC8_B2
# !a4 & _LC2_B2 & !_LC8_B2
# !_LC1_A6 & _LC2_B2 & !_LC8_B2
# a4 & _LC1_A6 & !_LC2_B2 & !_LC8_B2;
-- Node name is '|reg16:U5|:31' = '|reg16:U5|r16s12'
-- Equation name is '_LC2_B2', type is buried
_LC2_B2 = DFFE( _EQ018, _LC1_A5, GLOBAL(!start), VCC, VCC);
_EQ018 = _LC1_B2 & _LC4_B2 & _LC6_B2
# _LC1_B2 & !_LC4_B2 & !_LC6_B2
# !_LC1_B2 & _LC4_B2 & !_LC6_B2
# !_LC1_B2 & !_LC4_B2 & _LC6_B2;
-- Node name is '|reg16:U5|:30' = '|reg16:U5|r16s13'
-- Equation name is '_LC4_B2', type is buried
_LC4_B2 = DFFE( _EQ019, _LC1_A5, GLOBAL(!start), VCC, VCC);
_EQ019 = _LC1_B4 & _LC4_B2 & _LC6_B2
# _LC1_B4 & !_LC4_B2 & !_LC6_B2
# !_LC1_B2 & _LC1_B4
# _LC1_B2 & !_LC1_B4 & _LC4_B2 & !_LC6_B2
# _LC1_B2 & !_LC1_B4 & !_LC4_B2 & _LC6_B2;
-- Node name is '|reg16:U5|:29' = '|reg16:U5|r16s14'
-- Equation name is '_LC2_B4', type is buried
_LC2_B4 = DFFE( _EQ020, _LC1_A5, GLOBAL(!start), VCC, VCC);
_EQ020 = !_LC3_B4 & _LC4_B4 & _LC6_B4 & _LC7_B2
# _LC3_B4 & !_LC4_B4 & _LC6_B4 & _LC7_B2
# _LC3_B4 & _LC4_B4 & !_LC6_B4 & _LC7_B2
# !_LC3_B4 & !_LC4_B4 & !_LC6_B4 & _LC7_B2
# _LC3_B4 & _LC4_B4 & _LC6_B4 & !_LC7_B2
# !_LC3_B4 & !_LC4_B4 & _LC6_B4 & !_LC7_B2
# !_LC3_B4 & _LC4_B4 & !_LC6_B4 & !_LC7_B2
# _LC3_B4 & !_LC4_B4 & !_LC6_B4 & !_LC7_B2;
-- Node name is '|reg16:U5|:28' = '|reg16:U5|r16s15'
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = DFFE( _EQ021, _LC1_A5, GLOBAL(!start), VCC, VCC);
_EQ021 = !_LC3_B4 & _LC6_B4 & _LC7_B2
# _LC3_B4 & !_LC4_B4 & _LC7_B2
# !_LC3_B4 & _LC4_B4 & _LC7_B2
# !_LC3_B4 & _LC4_B4 & _LC6_B4
# _LC3_B4 & !_LC4_B4 & _LC6_B4
# _LC3_B4 & _LC4_B4 & !_LC6_B4
# _LC4_B4 & _LC6_B4 & !_LC7_B2
# _LC3_B4 & _LC6_B4 & !_LC7_B2
# _LC3_B4 & _LC4_B4 & !_LC7_B2;
-- Node name is '|sign8:U1|:9' = '|sign8:U1|cnt40'
-- Equation name is '_LC2_A13', type is buried
_LC2_A13 = DFFE( _EQ022, GLOBAL( clk), GLOBAL(!start), VCC, VCC);
_EQ022 = _LC1_A13 & _LC2_A13
# !_LC1_A13 & !_LC2_A13;
-- Node name is '|sign8:U1|:8' = '|sign8:U1|cnt41'
-- Equation name is '_LC3_A13', type is buried
_LC3_A13 = DFFE( _EQ023, GLOBAL( clk), GLOBAL(!start), VCC, VCC);
_EQ023 = !_LC1_A13 & _LC2_A13 & !_LC3_A13
# !_LC2_A13 & _LC3_A13
# _LC1_A13 & _LC3_A13;
-- Node name is '|sign8:U1|:7' = '|sign8:U1|cnt42'
-- Equation name is '_LC4_A13', type is buried
_LC4_A13 = DFFE( _EQ024, GLOBAL( clk), GLOBAL(!start), VCC, VCC);
_EQ024 = !_LC2_A13 & _LC4_A13
# !_LC3_A13 & _LC4_A13
# !_LC1_A13 & _LC2_A13 & _LC3_A13 & !_LC4_A13
# _LC1_A13 & _LC4_A13;
-- Node name is '|sign8:U1|:6' = '|sign8:U1|cnt43'
-- Equation name is '_LC1_A13', type is buried
_LC1_A13 = DFFE( _EQ025, GLOBAL( clk), GLOBAL(!start), VCC, VCC);
_EQ025 = _LC1_A13
# _LC2_A13 & _LC3_A13 & _LC4_A13;
-- Node name is '|sign8:U1|:175'
-- Equation name is '_LC2_A5', type is buried
_LC2_A5 = LCELL( _EQ026);
_EQ026 = clk & !_LC1_A13
# clk & start;
-- Node name is '|sign8:U1|:176'
-- Equation name is '_LC1_A5', type is buried
_LC1_A5 = LCELL( _EQ027);
_EQ027 = clk & !_LC1_A13 & !start;
-- Node name is '|sign8:U1|:182'
-- Equation name is '_LC7_A5', type is buried
_LC7_A5 = LCELL( _EQ028);
_EQ028 = _LC1_A13 & !start;
-- Node name is '|sreg8:U2|:19' = '|sreg8:U2|reg80'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = DFFE( _EQ029, _LC2_A5, VCC, VCC, VCC);
_EQ029 = _LC7_A6 & !start
# b0 & start;
-- Node name is '|sreg8:U2|:18' = '|sreg8:U2|reg81'
-- Equation name is '_LC7_A6', type is buried
_LC7_A6 = DFFE( _EQ030, _LC2_A5, VCC, VCC, VCC);
_EQ030 = _LC6_A6 & !start
# b1 & start;
-- Node name is '|sreg8:U2|:17' = '|sreg8:U2|reg82'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = DFFE( _EQ031, _LC2_A5, VCC, VCC, VCC);
_EQ031 = _LC5_A6 & !start
# b2 & start;
-- Node name is '|sreg8:U2|:16' = '|sreg8:U2|reg83'
-- Equation name is '_LC5_A6', type is buried
_LC5_A6 = DFFE( _EQ032, _LC2_A5, VCC, VCC, VCC);
_EQ032 = _LC4_A6 & !start
# b3 & start;
-- Node name is '|sreg8:U2|:15' = '|sreg8:U2|reg84'
-- Equation name is '_LC4_A6', type is buried
_LC4_A6 = DFFE( _EQ033, _LC2_A5, VCC, VCC, VCC);
_EQ033 = _LC3_A6 & !start
# b4 & start;
-- Node name is '|sreg8:U2|:14' = '|sreg8:U2|reg85'
-- Equation name is '_LC3_A6', type is buried
_LC3_A6 = DFFE( _EQ034, _LC2_A5, VCC, VCC, VCC);
_EQ034 = _LC2_A6 & !start
# b5 & start;
-- Node name is '|sreg8:U2|:13' = '|sreg8:U2|reg86'
-- Equation name is '_LC2_A6', type is buried
_LC2_A6 = DFFE( _EQ035, _LC2_A5, VCC, VCC, VCC);
_EQ035 = _LC8_A6 & !start
# b6 & start;
-- Node name is '|sreg8:U2|:12' = '|sreg8:U2|reg87'
-- Equation name is '_LC8_A6', type is buried
_LC8_A6 = DFFE( _EQ036, _LC2_A5, VCC, VCC, VCC);
_EQ036 = _LC8_A6 & !start
# b7 & start;
Project Information f:\zztt\vhdl\designtaxi_25\multi8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:02
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,137K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -