📄 multi8.rpt
字号:
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\multi8.rpt
multi8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - B 03 OR2 1 3 0 2 |add8:U4|add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry1
- 1 - B 03 OR2 1 3 0 2 |add8:U4|add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry2
- 8 - B 02 OR2 1 3 0 2 |add8:U4|add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry3
- 5 - B 03 AND2 1 2 0 2 |add8:U4|add4:U1|LPM_ADD_SUB:50|addcore:adder|:56
- 7 - B 04 OR2 1 3 0 2 |add8:U4|add4:U2|LPM_ADD_SUB:50|addcore:adder|pcarry1
- 6 - B 04 OR2 1 3 0 2 |add8:U4|add4:U2|LPM_ADD_SUB:50|addcore:adder|pcarry2
- 5 - B 04 AND2 1 2 0 1 |add8:U4|add4:U2|LPM_ADD_SUB:50|addcore:adder|:56
- 6 - B 02 OR2 s 2 2 0 3 |add8:U4|add4:U2|LPM_ADD_SUB:50|addcore:adder|~88~1
- 1 - B 04 OR2 1 3 0 2 |add8:U4|add4:U2|LPM_ADD_SUB:50|addcore:adder|:89
- 1 - B 02 OR2 1 3 0 3 |add8:U4|add4:U2|LPM_ADD_SUB:51|addcore:adder|:52
- 7 - B 02 OR2 0 4 0 2 |add8:U4|add4:U2|LPM_ADD_SUB:51|addcore:adder|:63
- 3 - B 04 AND2 1 1 0 2 |andari:U3|:553
- 4 - B 04 DFFE 0 4 1 1 |reg16:U5|r16s15 (|reg16:U5|:28)
- 2 - B 04 DFFE 0 5 1 2 |reg16:U5|r16s14 (|reg16:U5|:29)
- 4 - B 02 DFFE 0 4 1 3 |reg16:U5|r16s13 (|reg16:U5|:30)
- 2 - B 02 DFFE 0 4 1 4 |reg16:U5|r16s12 (|reg16:U5|:31)
- 3 - B 02 DFFE 1 4 1 2 |reg16:U5|r16s11 (|reg16:U5|:32)
- 5 - B 02 DFFE 1 4 1 2 |reg16:U5|r16s10 (|reg16:U5|:33)
- 4 - B 03 DFFE 1 4 1 2 |reg16:U5|r16s9 (|reg16:U5|:34)
- 3 - B 03 DFFE 1 4 1 2 |reg16:U5|r16s8 (|reg16:U5|:35)
- 2 - B 03 DFFE 1 3 1 1 |reg16:U5|r16s7 (|reg16:U5|:36)
- 8 - B 03 DFFE 0 2 1 1 |reg16:U5|r16s6 (|reg16:U5|:37)
- 3 - B 01 DFFE 0 2 1 1 |reg16:U5|r16s5 (|reg16:U5|:38)
- 2 - B 01 DFFE 0 2 1 1 |reg16:U5|r16s4 (|reg16:U5|:39)
- 1 - B 01 DFFE 0 2 1 1 |reg16:U5|r16s3 (|reg16:U5|:40)
- 5 - B 01 DFFE 0 2 1 1 |reg16:U5|r16s2 (|reg16:U5|:41)
- 7 - B 01 DFFE 0 2 1 1 |reg16:U5|r16s1 (|reg16:U5|:42)
- 8 - B 01 DFFE 0 2 1 0 |reg16:U5|r16s0 (|reg16:U5|:43)
- 1 - A 13 DFFE + 0 3 0 6 |sign8:U1|cnt43 (|sign8:U1|:6)
- 4 - A 13 DFFE + 0 3 0 1 |sign8:U1|cnt42 (|sign8:U1|:7)
- 3 - A 13 DFFE + 0 2 0 2 |sign8:U1|cnt41 (|sign8:U1|:8)
- 2 - A 13 DFFE + 0 1 0 3 |sign8:U1|cnt40 (|sign8:U1|:9)
- 2 - A 05 OR2 2 1 0 8 |sign8:U1|:175
- 1 - A 05 AND2 2 1 0 16 |sign8:U1|:176
- 7 - A 05 AND2 1 1 1 0 |sign8:U1|:182
- 8 - A 06 DFFE 2 1 0 1 |sreg8:U2|reg87 (|sreg8:U2|:12)
- 2 - A 06 DFFE 2 2 0 1 |sreg8:U2|reg86 (|sreg8:U2|:13)
- 3 - A 06 DFFE 2 2 0 1 |sreg8:U2|reg85 (|sreg8:U2|:14)
- 4 - A 06 DFFE 2 2 0 1 |sreg8:U2|reg84 (|sreg8:U2|:15)
- 5 - A 06 DFFE 2 2 0 1 |sreg8:U2|reg83 (|sreg8:U2|:16)
- 6 - A 06 DFFE 2 2 0 1 |sreg8:U2|reg82 (|sreg8:U2|:17)
- 7 - A 06 DFFE 2 2 0 1 |sreg8:U2|reg81 (|sreg8:U2|:18)
- 1 - A 06 DFFE 2 2 0 16 |sreg8:U2|reg80 (|sreg8:U2|:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\multi8.rpt
multi8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/ 96( 9%) 2/ 48( 4%) 0/ 48( 0%) 8/16( 50%) 1/16( 6%) 0/16( 0%)
B: 5/ 96( 5%) 10/ 48( 20%) 0/ 48( 0%) 4/16( 25%) 5/16( 31%) 0/16( 0%)
C: 1/ 96( 1%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 4/24( 16%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\multi8.rpt
multi8
** CLOCK SIGNALS **
Type Fan-out Name
LCELL 16 |sign8:U1|:176
LCELL 8 |sign8:U1|:175
INPUT 6 clk
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\multi8.rpt
multi8
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 31 start
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\multi8.rpt
multi8
** EQUATIONS **
a0 : INPUT;
a1 : INPUT;
a2 : INPUT;
a3 : INPUT;
a4 : INPUT;
a5 : INPUT;
a6 : INPUT;
a7 : INPUT;
b0 : INPUT;
b1 : INPUT;
b2 : INPUT;
b3 : INPUT;
b4 : INPUT;
b5 : INPUT;
b6 : INPUT;
b7 : INPUT;
clk : INPUT;
start : INPUT;
-- Node name is 'dout0'
-- Equation name is 'dout0', type is output
dout0 = _LC8_B1;
-- Node name is 'dout1'
-- Equation name is 'dout1', type is output
dout1 = _LC7_B1;
-- Node name is 'dout2'
-- Equation name is 'dout2', type is output
dout2 = _LC5_B1;
-- Node name is 'dout3'
-- Equation name is 'dout3', type is output
dout3 = _LC1_B1;
-- Node name is 'dout4'
-- Equation name is 'dout4', type is output
dout4 = _LC2_B1;
-- Node name is 'dout5'
-- Equation name is 'dout5', type is output
dout5 = _LC3_B1;
-- Node name is 'dout6'
-- Equation name is 'dout6', type is output
dout6 = _LC8_B3;
-- Node name is 'dout7'
-- Equation name is 'dout7', type is output
dout7 = _LC2_B3;
-- Node name is 'dout8'
-- Equation name is 'dout8', type is output
dout8 = _LC3_B3;
-- Node name is 'dout9'
-- Equation name is 'dout9', type is output
dout9 = _LC4_B3;
-- Node name is 'dout10'
-- Equation name is 'dout10', type is output
dout10 = _LC5_B2;
-- Node name is 'dout11'
-- Equation name is 'dout11', type is output
dout11 = _LC3_B2;
-- Node name is 'dout12'
-- Equation name is 'dout12', type is output
dout12 = _LC2_B2;
-- Node name is 'dout13'
-- Equation name is 'dout13', type is output
dout13 = _LC4_B2;
-- Node name is 'dout14'
-- Equation name is 'dout14', type is output
dout14 = _LC2_B4;
-- Node name is 'dout15'
-- Equation name is 'dout15', type is output
dout15 = _LC4_B4;
-- Node name is 'multend'
-- Equation name is 'multend', type is output
multend = _LC7_A5;
-- Node name is '|add8:U4|add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_B3', type is buried
_LC6_B3 = LCELL( _EQ001);
_EQ001 = _LC4_B3 & _LC5_B3
# a1 & _LC5_B3
# a1 & _LC1_A6 & _LC4_B3;
-- Node name is '|add8:U4|add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC1_B3', type is buried
_LC1_B3 = LCELL( _EQ002);
_EQ002 = _LC5_B2 & _LC6_B3
# a2 & _LC1_A6 & _LC6_B3
# a2 & _LC1_A6 & _LC5_B2;
-- Node name is '|add8:U4|add4:U1|LPM_ADD_SUB:50|addcore:adder|pcarry3' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC8_B2', type is buried
_LC8_B2 = LCELL( _EQ003);
_EQ003 = _LC1_B3 & _LC3_B2
# a3 & _LC1_A6 & _LC1_B3
# a3 & _LC1_A6 & _LC3_B2;
-- Node name is '|add8:U4|add4:U1|LPM_ADD_SUB:50|addcore:adder|:56' from file "addcore.tdf" line 308, column 28
-- Equation name is '_LC5_B3', type is buried
_LC5_B3 = LCELL( _EQ004);
_EQ004 = a0 & _LC1_A6 & _LC3_B3;
-- Node name is '|add8:U4|add4:U2|LPM_ADD_SUB:50|addcore:adder|pcarry1' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC7_B4', type is buried
_LC7_B4 = LCELL( _EQ005);
_EQ005 = _LC4_B2 & _LC5_B4
# a5 & _LC5_B4
# a5 & _LC1_A6 & _LC4_B2;
-- Node name is '|add8:U4|add4:U2|LPM_ADD_SUB:50|addcore:adder|pcarry2' from file "addcore.tdf" line 312, column 40
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = LCELL( _EQ006);
_EQ006 = _LC2_B4 & _LC7_B4
# a6 & _LC1_A6 & _LC7_B4
# a6 & _LC1_A6 & _LC2_B4;
-- Node name is '|add8:U4|add4:U2|LPM_ADD_SUB:50|addcore:adder|:56' from file "addcore.tdf" line 308, column 28
-- Equation name is '_LC5_B4', type is buried
_LC5_B4 = LCELL( _EQ007);
_EQ007 = a4 & _LC1_A6 & _LC2_B2;
-- Node name is '|add8:U4|add4:U2|LPM_ADD_SUB:50|addcore:adder|~88~1' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC6_B2', type is buried
-- synthesized logic cell
_LC6_B2 = LCELL( _EQ008);
_EQ008 = a5 & _LC1_A6 & !_LC2_B2
# !a4 & a5 & _LC1_A6
# a4 & !a5 & _LC1_A6 & _LC2_B2;
-- Node name is '|add8:U4|add4:U2|LPM_ADD_SUB:50|addcore:adder|:89' from file "addcore.tdf" line 316, column 67
-- Equation name is '_LC1_B4', type is buried
_LC1_B4 = LCELL( _EQ009);
_EQ009 = a6 & _LC1_A6 & _LC2_B4 & _LC7_B4
# !a6 & !_LC2_B4 & _LC7_B4
# !_LC1_A6 & !_LC2_B4 & _LC7_B4
# !a6 & _LC2_B4 & !_LC7_B4
# !_LC1_A6 & _LC2_B4 & !_LC7_B4
# a6 & _LC1_A6 & !_LC2_B4 & !_LC7_B4;
-- Node name is '|add8:U4|add4:U2|LPM_ADD_SUB:51|addcore:adder|:52' from file "addcore.tdf" line 308, column 28
-- Equation name is '_LC1_B2', type is buried
_LC1_B2 = LCELL( _EQ010);
_EQ010 = !a4 & _LC2_B2 & _LC8_B2
# !_LC1_A6 & _LC2_B2 & _LC8_B2
# a4 & _LC1_A6 & !_LC2_B2 & _LC8_B2;
-- Node name is '|add8:U4|add4:U2|LPM_ADD_SUB:51|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B2', type is buried
_LC7_B2 = LCELL( _EQ011);
_EQ011 = _LC1_B2 & _LC1_B4 & _LC4_B2 & !_LC6_B2
# _LC1_B2 & _LC1_B4 & !_LC4_B2 & _LC6_B2;
-- Node name is '|andari:U3|:553'
-- Equation name is '_LC3_B4', type is buried
_LC3_B4 = LCELL( _EQ012);
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