📄 decoder3_8.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity decoder3_8 is
port(
quiclk:in std_logic;
wei8:out std_logic_vector(7 downto 0)
);
end decoder3_8;
architecture func of decoder3_8 is
signal choice :std_logic_vector(2 downto 0);
begin
process(quiclk)
begin
if(quiclk'event and quiclk='1') then
if(choice="111") then
choice<="000";
else
choice<=choice+1;
end if;
end if;
end process;
with choice select
wei8<="10000000" when "000",
"01000000" when "001",
"00100000" when "010",
"00010000" when "011",
"00001000" when "100",
"00000100" when "101",
"00000010" when "110",
"00000001" when "111",
"00000000" when others;
end func;
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