📄 sign8.rpt
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Device-Specific Information: f:\zztt\vhdl\designtaxi_25\sign8.rpt
sign8
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 02 LCELL s 1 0 1 0 rstall~1
- 1 - A 01 DFFE + 0 3 0 5 cnt43 (:6)
- 2 - A 01 DFFE + 0 3 0 1 cnt42 (:7)
- 4 - A 01 DFFE + 0 2 0 2 cnt41 (:8)
- 6 - A 01 DFFE + 0 1 0 3 cnt40 (:9)
- 3 - A 01 OR2 s 1 1 1 0 ~175~1
- 5 - A 01 OR2 2 1 1 0 :175
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\sign8.rpt
sign8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\sign8.rpt
sign8
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 5 clk
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\sign8.rpt
sign8
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 7 start
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\sign8.rpt
sign8
** EQUATIONS **
clk : INPUT;
start : INPUT;
-- Node name is 'clkout'
-- Equation name is 'clkout', type is output
clkout = _LC5_A1;
-- Node name is ':9' = 'cnt40'
-- Equation name is 'cnt40', location is LC6_A1, type is buried.
cnt40 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!start), VCC, VCC);
_EQ001 = cnt40 & cnt43
# !cnt40 & !cnt43;
-- Node name is ':8' = 'cnt41'
-- Equation name is 'cnt41', location is LC4_A1, type is buried.
cnt41 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!start), VCC, VCC);
_EQ002 = cnt40 & !cnt41 & !cnt43
# !cnt40 & cnt41
# cnt41 & cnt43;
-- Node name is ':7' = 'cnt42'
-- Equation name is 'cnt42', location is LC2_A1, type is buried.
cnt42 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!start), VCC, VCC);
_EQ003 = !cnt40 & cnt42
# !cnt41 & cnt42
# cnt40 & cnt41 & !cnt42 & !cnt43
# cnt42 & cnt43;
-- Node name is ':6' = 'cnt43'
-- Equation name is 'cnt43', location is LC1_A1, type is buried.
cnt43 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!start), VCC, VCC);
_EQ004 = cnt43
# cnt40 & cnt41 & cnt42;
-- Node name is 'multend'
-- Equation name is 'multend', type is output
multend = !_LC3_A1;
-- Node name is 'rstall'
-- Equation name is 'rstall', type is output
rstall = _LC1_A2;
-- Node name is 'rstall~1'
-- Equation name is 'rstall~1', location is LC1_A2, type is buried.
-- synthesized logic cell
_LC1_A2 = LCELL( start);
-- Node name is '~175~1'
-- Equation name is '~175~1', location is LC3_A1, type is buried.
-- synthesized logic cell
_LC3_A1 = LCELL( _EQ005);
_EQ005 = start
# !cnt43;
-- Node name is ':175'
-- Equation name is '_LC5_A1', type is buried
_LC5_A1 = LCELL( _EQ006);
_EQ006 = clk & start
# clk & !cnt43;
Project Information f:\zztt\vhdl\designtaxi_25\sign8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,242K
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