sign8.vhd

出租车计费器,VHDL实现

LIBRARY  IEEE;
USE  IEEE.STD_LOGIC_1164.ALL;
USE  IEEE.STD_LOGIC_UNSIGNED.ALL; 
ENTITY sign8 IS
    PORT(
           clk,start:IN STD_LOGIC;
        clkout,rstall,multend:OUT STD_LOGIC);
END  sign8;

ARCHITECTURE  execute  OF sign8  IS
  SIGNAL  cnt4:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
rstall<=start;
      PROCESS(clk,start)
      BEGIN
          IF start='1'THEN
            cnt4<="0000";
          ELSIF clk'EVENT AND clk='1'THEN
              IF cnt4<8 THEN
              cnt4<=cnt4+1;
              END IF;
           END IF;
      END PROCESS;
      PROCESS(clk,cnt4,start)
      BEGIN
          IF start='0'THEN
              IF cnt4<8 THEN
                 clkout<=clk;
                 multend<='0'; 
              ELSE
                 clkout<='0';
                 multend<='1'; 
              END IF;
          ELSE 
                clkout<=clk;
                multend<='0'; 
          END IF;
      END  PROCESS;
END execute;