📄 count60.rpt
字号:
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\count60.rpt
count60
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 3/ 96( 3%) 5/ 48( 10%) 0/ 48( 0%) 0/16( 0%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\count60.rpt
count60
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 6 clk
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\count60.rpt
count60
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 6 clr
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\count60.rpt
count60
** EQUATIONS **
clk : INPUT;
clr : INPUT;
start : INPUT;
-- Node name is 'hor'
-- Equation name is 'hor', type is output
hor = _LC1_A1;
-- Node name is ':16' = 'min_tmp0'
-- Equation name is 'min_tmp0', location is LC5_A2, type is buried.
min_tmp0 = DFFE( _EQ001, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ001 = min_tmp0 & start
# !min_tmp0 & !start;
-- Node name is ':15' = 'min_tmp1'
-- Equation name is 'min_tmp1', location is LC6_A2, type is buried.
min_tmp1 = DFFE( _EQ002, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ002 = !_LC1_A1 & !min_tmp0 & min_tmp1
# !_LC1_A1 & min_tmp0 & !min_tmp1 & !start
# min_tmp1 & start;
-- Node name is ':14' = 'min_tmp2'
-- Equation name is 'min_tmp2', location is LC3_A3, type is buried.
min_tmp2 = DFFE( _EQ003, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ003 = !_LC1_A1 & !_LC1_A2 & min_tmp2
# !_LC1_A1 & _LC1_A2 & !min_tmp2 & !start
# min_tmp2 & start;
-- Node name is ':13' = 'min_tmp3'
-- Equation name is 'min_tmp3', location is LC3_A1, type is buried.
min_tmp3 = DFFE( _EQ004, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ004 = !_LC1_A1 & !_LC2_A1 & min_tmp3
# !_LC1_A1 & _LC2_A1 & !min_tmp3 & !start
# min_tmp3 & start;
-- Node name is ':12' = 'min_tmp4'
-- Equation name is 'min_tmp4', location is LC4_A1, type is buried.
min_tmp4 = DFFE( _EQ005, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ005 = !_LC1_A1 & !_LC8_A1 & min_tmp4
# !_LC1_A1 & _LC8_A1 & !min_tmp4 & !start
# min_tmp4 & start;
-- Node name is ':11' = 'min_tmp5'
-- Equation name is 'min_tmp5', location is LC5_A1, type is buried.
min_tmp5 = DFFE( _EQ006, GLOBAL( clk), GLOBAL(!clr), VCC, VCC);
_EQ006 = !_LC1_A1 & !_LC7_A1 & min_tmp5
# !_LC1_A1 & _LC7_A1 & !min_tmp5 & !start
# min_tmp5 & start;
-- Node name is 'min0'
-- Equation name is 'min0', type is output
min0 = min_tmp0;
-- Node name is 'min1'
-- Equation name is 'min1', type is output
min1 = min_tmp1;
-- Node name is 'min2'
-- Equation name is 'min2', type is output
min2 = min_tmp2;
-- Node name is 'min3'
-- Equation name is 'min3', type is output
min3 = min_tmp3;
-- Node name is 'min4'
-- Equation name is 'min4', type is output
min4 = min_tmp4;
-- Node name is 'min5'
-- Equation name is 'min5', type is output
min5 = min_tmp5;
-- Node name is '|LPM_ADD_SUB:104|addcore:adder|:63' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_A2', type is buried
!_LC1_A2 = _LC1_A2~NOT;
_LC1_A2~NOT = LCELL( _EQ007);
_EQ007 = !min_tmp1
# !min_tmp0;
-- Node name is '|LPM_ADD_SUB:104|addcore:adder|:67' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_A1', type is buried
_LC2_A1 = LCELL( _EQ008);
_EQ008 = _LC1_A2 & min_tmp2;
-- Node name is '|LPM_ADD_SUB:104|addcore:adder|:71' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_A1', type is buried
_LC8_A1 = LCELL( _EQ009);
_EQ009 = _LC1_A2 & min_tmp2 & min_tmp3;
-- Node name is '|LPM_ADD_SUB:104|addcore:adder|:75' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_A1', type is buried
_LC7_A1 = LCELL( _EQ010);
_EQ010 = _LC1_A2 & min_tmp2 & min_tmp3 & min_tmp4;
-- Node name is '~67~1'
-- Equation name is '~67~1', location is LC6_A1, type is buried.
-- synthesized logic cell
_LC6_A1 = LCELL( _EQ011);
_EQ011 = !min_tmp4
# !min_tmp5
# !min_tmp3;
-- Node name is ':67'
-- Equation name is '_LC1_A1', type is buried
!_LC1_A1 = _LC1_A1~NOT;
_LC1_A1~NOT = LCELL( _EQ012);
_EQ012 = min_tmp2
# !_LC1_A2
# _LC6_A1;
Project Information f:\zztt\vhdl\designtaxi_25\count60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 13,816K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -