📄 sreg8.rpt
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** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 01 DFFE + 2 0 0 1 reg87 (:12)
- 8 - A 01 DFFE + 2 1 0 1 reg86 (:13)
- 2 - A 01 DFFE + 2 1 0 1 reg85 (:14)
- 3 - A 01 DFFE + 2 1 0 1 reg84 (:15)
- 4 - A 01 DFFE + 2 1 0 1 reg83 (:16)
- 6 - A 01 DFFE + 2 1 0 1 reg82 (:17)
- 7 - A 01 DFFE + 2 1 0 1 reg81 (:18)
- 5 - A 01 DFFE + 2 1 1 0 reg80 (:19)
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\sreg8.rpt
sreg8
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 4/ 96( 4%) 1/ 48( 2%) 0/ 48( 0%) 4/16( 25%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\sreg8.rpt
sreg8
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 8 clk
Device-Specific Information: f:\zztt\vhdl\designtaxi_25\sreg8.rpt
sreg8
** EQUATIONS **
clk : INPUT;
din0 : INPUT;
din1 : INPUT;
din2 : INPUT;
din3 : INPUT;
din4 : INPUT;
din5 : INPUT;
din6 : INPUT;
din7 : INPUT;
load : INPUT;
-- Node name is 'qb'
-- Equation name is 'qb', type is output
qb = reg80;
-- Node name is ':19' = 'reg80'
-- Equation name is 'reg80', location is LC5_A1, type is buried.
reg80 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !load & reg81
# din0 & load;
-- Node name is ':18' = 'reg81'
-- Equation name is 'reg81', location is LC7_A1, type is buried.
reg81 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = !load & reg82
# din1 & load;
-- Node name is ':17' = 'reg82'
-- Equation name is 'reg82', location is LC6_A1, type is buried.
reg82 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !load & reg83
# din2 & load;
-- Node name is ':16' = 'reg83'
-- Equation name is 'reg83', location is LC4_A1, type is buried.
reg83 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = !load & reg84
# din3 & load;
-- Node name is ':15' = 'reg84'
-- Equation name is 'reg84', location is LC3_A1, type is buried.
reg84 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !load & reg85
# din4 & load;
-- Node name is ':14' = 'reg85'
-- Equation name is 'reg85', location is LC2_A1, type is buried.
reg85 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !load & reg86
# din5 & load;
-- Node name is ':13' = 'reg86'
-- Equation name is 'reg86', location is LC8_A1, type is buried.
reg86 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !load & reg87
# din6 & load;
-- Node name is ':12' = 'reg87'
-- Equation name is 'reg87', location is LC1_A1, type is buried.
reg87 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = !load & reg87
# din7 & load;
Project Information f:\zztt\vhdl\designtaxi_25\sreg8.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 15,670K
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