📄 andari.vhd
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LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY andari IS
PORT(
abin:IN STD_LOGIC;
din:IN STD_LOGIC_VECTOR(7 DOWNTO 0);
dout:OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END andari;
ARCHITECTURE execute OF andari IS
BEGIN
PROCESS(abin,din)
BEGIN
FOR i IN 0 TO 7 LOOP
dout(i)<=din(i) AND abin;
END LOOP;
END PROCESS;
END execute;
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